公开(公告)号：US20060083341A1

公开(公告)日：2006-04-20

申请号：US10968735

申请日：2004-10-19

申请人： Samuel Naffziger ,  Steven Liepe

发明人： Samuel Naffziger ,  Steven Liepe

IPC分类号： H04L7/00

CPC分类号： H03K5/15046

摘要： One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

公开(公告)号：US20050223251A1

公开(公告)日：2005-10-06

申请号：US10818974

申请日：2004-04-06

申请人： Steven Liepe ,  Samuel Naffziger

发明人： Steven Liepe ,  Samuel Naffziger

IPC分类号： G06F1/26 ,  G06F1/28 ,  G06F11/00

CPC分类号： H03K19/0008 ,  G06F11/00

摘要： Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F

摘要翻译： 公开了用于增加集成电路的可靠性的技术。 在一个实施例中，集成电路包括核心芯片电路。 集成电路包括用于增加提供给核心芯片电路的电源电压V的装置，例如通过将电压V增加到最大值。 该集成电路还包括用于识别其中C是开关电容的时钟频率F的装置，其中，P＆lt; P＆lt; max 是核心芯片电路的预定最大功耗。 集成电路还包括用于向电路提供具有频率F的时钟信号的装置。