摘要:
A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要:
A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要:
A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要:
Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.
摘要:
Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要:
An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
摘要:
Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要:
A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.
摘要:
A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.
摘要:
The invention provides apparatuses and techniques for controlling flow between a manifold and two or more connecting microchannels. Flow between plural connecting microchannels, that share a common manifold, can be made more uniform by the use of flow straighteners and distributors that equalize flow in connecting channels. Alternatively, flow can be made more uniform by sections of narrowed diameter within the channels. Methods of making apparatus and methods of conducting unit operations in connecting channels are also described.