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1.发明授权公开(公告)号：US08572141B2
公开(公告)日：2013-10-29
申请号：US12051333
申请日：2008-03-19
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译： 使用十进制浮点（DFP）单位执行固定点指令。 接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。 通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。 确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。 对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。
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2.发明申请METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS 有权方法，硬件产品和计算机程序产品，用于使用十进制浮点单元执行固定点说明公开(公告)号：US20090240753A1
公开(公告)日：2009-09-24
申请号：US12051333
申请日：2008-03-19
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译： 使用十进制浮点（DFP）单位执行固定点指令。 接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。 通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。 确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。 对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。
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3.发明申请ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL AND DENSELY PACKED DECIMAL CONVERSIONS 失效在二进制编码的十进制和密封包装的十进制转换中使用奇偶校验的错误检测公开(公告)号：US20100306632A1
公开(公告)日：2010-12-02
申请号：US12472519
申请日：2009-05-27
摘要： Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.
摘要翻译： 使用二进制编码十进制（BCD）和密集十进制（DPD）转换中的奇偶校验的误差检测，包括具有由处理电路可读的有形存储介质的计算机程序产品，并且存储由处理电路执行以执行方法的指令。 该方法包括以第一格式接收格式化的十进制数据，格式化的十进制数据由DPD格式数据或BCD格式数据组成。 通过将接收到的数据转换成格式化的十进制数据的第二格式，并且通过确定第二格式的数据的奇偶校验来生成一个或多个第一奇偶校验位。 从接收的数据直接生成一个或多个第二奇偶校验位。 响应于第一奇偶校验位不等于第二奇偶校验位，错误标志被设置为指示第二格式的数据中的错误。
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4.发明授权Error detection using parity compensation in binary coded decimal and densely packed decimal conversions 失效使用二进制编码十进制和密集十进制转换中的奇偶补偿进行错误检测公开(公告)号：US08286061B2
公开(公告)日：2012-10-09
申请号：US12472519
申请日：2009-05-27
IPC分类号： H03M13/00
摘要： Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.
摘要翻译： 使用二进制编码十进制（BCD）和密集十进制（DPD）转换中的奇偶校验的误差检测，包括具有由处理电路可读的有形存储介质的计算机程序产品，并且存储由处理电路执行以执行方法的指令。 该方法包括以第一格式接收格式化的十进制数据，格式化的十进制数据由DPD格式数据或BCD格式数据组成。 通过将接收到的数据转换成格式化的十进制数据的第二格式，并且通过确定第二格式的数据的奇偶校验来生成一个或多个第一奇偶校验位。 从接收的数据直接生成一个或多个第二奇偶校验位。 响应于第一奇偶校验位不等于第二奇偶校验位，错误标志被设置为指示第二格式的数据中的错误。
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公开(公告)号：US20090049353A1
公开(公告)日：2009-02-19
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译： 提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。 该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序 锁存器 创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序 连线到另一个锁存器的扫描输出。
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公开(公告)号：US07721171B2
公开(公告)日：2010-05-18
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/28
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译： 提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。 该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序 锁存器 创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序 连接到另一个锁存器的扫描输出。
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公开(公告)号：US06170078A
公开(公告)日：2001-01-02
申请号：US09032567
申请日：1998-02-27
IPC分类号： G06F1750
CPC分类号： G01R31/318342
摘要： A system and method for the fault simulation testing of circuits by using a behavioral model is provided. The behavioral model includes a fault bus, decoder, and input and output ports. The decoder decodes mapping fault values, which are applied to the fault bus, to either a no-fault or to a specific fault which is internally encoded into the behavioral model. Accordingly, a single behavioral model can be used to dynamically model a fault-free circuit or machine and one or more faulty circuits or machines based on the mapping fault data applied to each model's fault bus. A fault simulation tool applies test simulation data having mapping fault and test parameter data to at least two identically coded behavioral models (i.e., a fault-free model and a faulty model, as defined by the applied mapping fault data). Output data are generated by each behavioral model and recorded by the fault simulation tool. A comparison of the output data of the fault-free behavioral model and the at least one faulty behavioral model is performed to determine whether the test pattern data detected differences therebetween.
摘要翻译： 提供了一种通过使用行为模型对电路进行故障模拟测试的系统和方法。 行为模型包括故障总线，解码器和输入和输出端口。 解码器将应用于故障总线的故障值映射到内部编码到行为模型中的无故障或特定故障。 因此，可以使用单个行为模型来基于应用于每个模型的故障总线的映射故障数据来动态地建模无故障电路或机器以及一个或多个故障电路或机器。 故障仿真工具将具有映射故障和测试参数数据的测试仿真数据应用于至少两个相同编码的行为模型（即，由应用的映射故障数据定义的无故障模型和故障模型）。 输出数据由每个行为模型生成并由故障模拟工具记录。 执行无故障行为模型的输出数据与至少一个故障行为模型的比较，以确定测试模式数据是否检测到差异。
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