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公开(公告)号：US08006153B2
公开(公告)日：2011-08-23
申请号：US12197691
申请日：2008-08-25
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译： 提供了一种方法，装置和计算机程序以利用用于多个目的的内置自检（BIST）锁存器。 通常，BIST锁存器是单一目的。 因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。 然而，通过使用单独的锁存器，大量的区域丢失。 因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。
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公开(公告)号：US20080313512A1
公开(公告)日：2008-12-18
申请号：US12197691
申请日：2008-08-25
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译： 提供了一种方法，装置和计算机程序以利用用于多个目的的内置自检（BIST）锁存器。 通常，BIST锁存器是单一目的。 因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。 然而，通过使用单独的锁存器，大量的区域丢失。 因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。
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公开(公告)号：US07574642B2
公开(公告)日：2009-08-11
申请号：US11101615
申请日：2005-04-07
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译： 提供了一种用于多种用途的内置自检（BIST）锁存器的方法。 通常，BIST锁存器是单一目的。 因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。 然而，通过使用单独的锁存器，大量的区域丢失。 因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。
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4.发明授权Methods and apparatus for reducing power consumption in a processor using clock signal control 有权使用时钟信号控制来降低处理器功耗的方法和装置公开(公告)号：US07233188B1
公开(公告)日：2007-06-19
申请号：US11318228
申请日：2005-12-22
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
摘要翻译： 方法和装置提供：产生指示睡眠模式的第一基本上稳定的状态逻辑电平的控制信号，以及指示正常模式的第二基本稳定的逻辑电平; 当控制信号处于第一逻辑电平时产生处于基本稳态零电平的门信号，并且当控制信号处于第二逻辑电平时以当地时钟频率振荡; 根据门信号从系统时钟信号产生本地时钟信号; 并且在控制信号的原点与产生栅极信号的位置之间插入至少一个信号传播锁存电路。
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