Encoder using low density parity check codes and encoding method thereof
    1.
    发明授权
    Encoder using low density parity check codes and encoding method thereof 失效
    使用低密度奇偶校验码的编码器及其编码方法

    公开(公告)号:US07178085B2

    公开(公告)日:2007-02-13

    申请号:US10535925

    申请日:2003-11-21

    IPC分类号: H03M13/00

    摘要: An encoder using LDPC (low density parity check) codes, and an encoding method. The encoder comprises a parity check matrix generator for generating a parity check matrix H; and a codeword generator for processing the parity check matrix H to generate a codeword, and the codeword generator comprises: an AB analyzer for analyzing the parity check matrix H into matrixes A and B; a pivoting unit for pivoting the parity check matrix H; a bit-reversing unit for bit-reversing the pivoted matrix; an LU analyzer for analyzing the matrix A into matrixes L and U; and a codeword generator unit for performing a logical operation on the matrixes A, B, L and U. A bit-reversing method is used to effectively generate a parity check matrix having a high girth by using a regular encoder.

    摘要翻译: 使用LDPC(低密度奇偶校验)码的编码器,以及编码方法。 编码器包括用于产生奇偶校验矩阵H的奇偶校验矩阵发生器; 以及用于处理奇偶校验矩阵H以生成码字的码字生成器,并且码字生成器包括:用于将奇偶校验矩阵H分析为矩阵A和B的AB分析器; 用于枢转奇偶校验矩阵H的枢转单元; 用于对所述枢转矩阵进行位反转的位反转单元; 用于将矩阵A分解为矩阵L和U的LU分析器; 以及用于对矩阵A,B,L和U执行逻辑运算的码字发生器单元。使用位反转方法通过使用常规编码器来有效地生成具有高周长的奇偶校验矩阵。

    Encoder using low density parity check codes and encoding method thereof
    2.
    发明申请
    Encoder using low density parity check codes and encoding method thereof 失效
    使用低密度奇偶校验码的编码器及其编码方法

    公开(公告)号:US20060053359A1

    公开(公告)日:2006-03-09

    申请号:US10535925

    申请日:2003-11-21

    IPC分类号: H03M13/00 H04L27/36

    摘要: An encoder using LDPC (low density parity check) codes, and an encoding method. The encoder comprises a parity check matrix generator for generating a parity check matrix H; and a codeword generator for processing the parity check matrix H to generate a codeword, and the codeword generator comprises: an AB analyzer for analyzing the parity check matrix H into matrixes A and B; a pivoting unit for pivoting the parity check matrix H; a bit-reversing unit for bit-reversing the pivoted matrix; an LU analyzer for analyzing the matrix A into matrixes L and U; and a codeword generator unit for performing a logical operation on the matrixes A, B, L and U. A bit-reversing method is used to effectively generate a parity check matrix having a high girth by using a regular encoder.

    摘要翻译: 使用LDPC(低密度奇偶校验)码的编码器,以及编码方法。 编码器包括用于产生奇偶校验矩阵H的奇偶校验矩阵发生器; 以及用于处理奇偶校验矩阵H以生成码字的码字生成器,并且码字生成器包括:用于将奇偶校验矩阵H分析为矩阵A和B的AB分析器; 用于枢转奇偶校验矩阵H的枢转单元; 用于对所述枢转矩阵进行位反转的位反转单元; 用于将矩阵A分解为矩阵L和U的LU分析器; 以及用于对矩阵A,B,L和U执行逻辑运算的码字发生器单元。使用位反转方法通过使用常规编码器来有效地生成具有高周长的奇偶校验矩阵。

    Demodulation apparatus for efficiently embodying adaptive modulation and coding method in OFDMA based packet communication system and method thereof
    3.
    发明授权
    Demodulation apparatus for efficiently embodying adaptive modulation and coding method in OFDMA based packet communication system and method thereof 有权
    一种用于在基于OFDMA的分组通信系统中有效实现自适应调制和编码方法的解调装置及其方法

    公开(公告)号:US08068510B2

    公开(公告)日:2011-11-29

    申请号:US10583167

    申请日:2004-11-03

    IPC分类号: H04Q11/02

    摘要: Disclosed is a demodulation apparatus for receiving signals by an adaptive modulation and coding method, and demodulating the signals, in an OFDMA based packet communication system, comprising: a QAM demapper for performing QAM demapping to the received signals by a modulation method using a maximum modulation ratio, until modulation methods for each of sub-channels are analyzed; a slot buffer for storing the data outputted from the QAM demapper; a channel decoder for decoding the data stored in the slot buffer and analyzing modulation methods for each sub-channels and transferring the analyzed modulation methods to the QAM demapper; and in at the same time, reading valid data from the data stored in the slot buffer, based on the analyzed modulation methods for each sub-channels, and demodulating the valid data.

    摘要翻译: 公开了一种用于在基于OFDMA的分组通信系统中通过自适应调制和编码方法接收信号并解调信号的解调装置,包括:QAM解映射器,用于通过使用最大调制的调制方法对所接收的信号进行QAM解映射 比例,直到分析每个子信道的调制方法; 用于存储从QAM解映射器输出的数据的时隙缓冲器; 用于解码存储在时隙缓冲器中的数据并分析每个子信道的调制方法并将分析的调制方法传送到QAM解映射器的信道解码器; 并且同时,基于针对每个子信道的分析的调制方法和解调有效数据,从存储在时隙缓冲器中的数据读取有效数据。

    Low density parity check encoder using costas array, and channel encoder of high speed portable internet system comprising the same and channel encoding method
    4.
    发明授权
    Low density parity check encoder using costas array, and channel encoder of high speed portable internet system comprising the same and channel encoding method 有权
    使用costas阵列的低密度奇偶校验编码器和包含相同和通道编码方法的高速便携式互联网系统的通道编码器

    公开(公告)号:US07954035B2

    公开(公告)日:2011-05-31

    申请号:US11722214

    申请日:2005-03-25

    IPC分类号: H03M13/00

    CPC分类号: H03M13/116 H03M13/1177

    摘要: The present invention provides an LDPC encoder, a channel encoder of a portable internet system including the LDPC encoder, and an encoding method thereof. The LDPC encoder according to the present invention generates a Costas array, shifts it, generates an analogous circulation parity check matrix having a repeated pattern from the shifted Costas array, and performs encoding by using the parity check matrix. With this LDPC encoder, complexity of encoding system may be reduced.

    摘要翻译: 本发明提供一种LDPC编码器,包括LDPC编码器的便携式互联网系统的信道编码器及其编码方法。 根据本发明的LDPC编码器生成Costas阵列,将其移位,从移位的Costas阵列生成具有重复模式的类似循环奇偶校验矩阵,并通过使用奇偶校验矩阵进行编码。 利用该LDPC编码器,可以减少编码系统的复杂性。

    Method of selecting candidate vector and method of detecting transmission symbol
    5.
    发明授权
    Method of selecting candidate vector and method of detecting transmission symbol 有权
    选择候选矢量的方法和检测传输符号的方法

    公开(公告)号:US08054909B2

    公开(公告)日:2011-11-08

    申请号:US12141539

    申请日:2008-06-18

    IPC分类号: H04L27/00 G06Q30/00

    摘要: The present invention relates to a method of detecting a candidate vector and a method of detecting a transmission symbol using the same. According to an embodiment of the present invention, in a multiple input multiple output (MIMO) system using spatial multiplexing (SM), a receiver selects candidate vectors corresponding to a layer located at a last row among a plurality of rearranged layers, and sequentially ranks constellation dots of a next layer for each of the selected candidate vectors. Then, a plurality of arbitrary constellation dots are selected from the ranked constellation dots, accumulated costs of the arbitrary constellation dots are calculated, and a candidate vector is selected in correspondence with a constellation dot having a minimal accumulated cost. Then, a new arbitrary constellation dot is selected in place of the constellation dot selected as the candidate vector, an accumulated cost of the selected arbitrary constellation dot is compared with accumulated costs of the other arbitrary constellation dots, and another candidate vector is selected.

    摘要翻译: 本发明涉及检测候选向量的方法和使用其的发送符号的检测方法。 根据本发明的实施例,在使用空间复用(SM)的多输入多输出(MIMO)系统中,接收机选择与多个重排层中位于最后一行的层相对应的候选向量,并且顺次排列 每个所选候选向量的下一层的星座点。 然后,从分级星座点中选择多个任意星座点,计算任意星座点的累积成本,并且与具有最小累积成本的星座点对应地选择候选矢量。 然后,代替选择为候选矢量的星座点,选择新的任意星座点,将所选择的任意星座点的累积成本与其他任意星座点的累积成本进行比较,并选择另一候选矢量。

    Subcarrier allocation apparatus and method, subcarrier de-allocation apparatus and method in OFDM system
    6.
    发明授权
    Subcarrier allocation apparatus and method, subcarrier de-allocation apparatus and method in OFDM system 有权
    OFDM系统中的副载波分配装置和方法,子载波去分配装置和方法

    公开(公告)号:US08134914B2

    公开(公告)日:2012-03-13

    申请号:US11721136

    申请日:2005-11-10

    IPC分类号: H04J11/00

    摘要: A subcarrier allocating apparatus allocating data to be transmitted to a plurality of orthogonal subcarriers in an orthogonal frequency division multiplexing (OFDM) system is provided. The apparatus includes a logical index generator generating a logical index for allocating a data subcarrier to a physical index, the logical index being included with only data subcarriers and the physical index indicating a location of a substantial subcarrier within a symbol, an intermediate index converter converting the logical index into an intermediate index by performing a given operation on the generated logical index and a pilot location constant, and a physical index converter converting the intermediate index into a physical index based on the number of data subcarriers on the left and right sides of a null subcarrier for insertion of a guard interval formed by the null subcarrier.

    摘要翻译: 提供了一种在正交频分复用(OFDM)系统中分配要发送到多个正交子载波的数据的副载波分配装置。 该装置包括逻辑索引生成器,其生成用于将数据子载波分配给物理索引的逻辑索引,所述逻辑索引仅包括数据子载波,并且所述物理索引指示符号内的实质子载波的位置,中间索引转换器转换 通过对所生成的逻辑索引和导频位置常数执行给定的操作而将中间索引的逻辑索引转换成中间索引;以及物理索引转换器,其基于左侧和右侧的数据子载波的数量将中间索引转换为物理索引 用于插入由无效副载波形成的保护间隔的无效副载波。

    Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method
    7.
    发明授权
    Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method 有权
    奇偶校验矩阵存储方法,块LDPC编码方法,以及使用奇偶校验矩阵存储方法的装置

    公开(公告)号:US08190967B2

    公开(公告)日:2012-05-29

    申请号:US11861884

    申请日:2007-09-26

    IPC分类号: H03M13/11 H03M13/33

    CPC分类号: H03M13/1185 H03M13/6561

    摘要: The present invention relates to a low density parity check (LDPC) encoding method and an apparatus thereof. In the LDPC encoding method, a matrix multiplication corresponding to ET−1 and T−1 is eliminated according to a structural characteristic in an encoding process. Accordingly, shift weights that are not −1 among shift weights corresponding to partial blocks A, B, and C of a parity check matrix are used to perform an encoding operation, and a cyclic shift operation of an information unit block is performed in parallel so that a first parity block and a second parity block may be simultaneously generated.

    摘要翻译: 本发明涉及一种低密度奇偶校验(LDPC)编码方法及其装置。 在LDPC编码方法中,根据编码处理中的结构特征,消除对应于ET-1和T-1的矩阵乘法。 因此,使用对应于奇偶校验矩阵的部分块A,B和C的移位权重之中不为-1的移动权重进行编码操作,并行执行信息单元块的循环移位操作 可以同时生成第一奇偶校验块和第二奇偶校验块。

    Method of calculating soft value and method of detecting transmission signal
    8.
    发明授权
    Method of calculating soft value and method of detecting transmission signal 有权
    计算软值的方法和检测传输信号的方法

    公开(公告)号:US08081577B2

    公开(公告)日:2011-12-20

    申请号:US12141673

    申请日:2008-06-18

    IPC分类号: H04L12/56 H04J1/16

    摘要: The present invention relates to a method of calculating a soft value and a method of detecting a transmission signal. The present invention estimates a channel on the basis of a received signal and rearranges a plurality of data streams. Further, a plurality of substitute vectors are selected from the rearranged data streams and a metric corresponding to each of the substitute vector is calculated. Further, a threshold value is calculated from a metric calculated for each of the substitute vectors and a soft value of each bit of a transmission signal is calculated from the metric and threshold value corresponding to each of the substitute vectors.

    摘要翻译: 本发明涉及计算软值的方法和检测发送信号的方法。 本发明基于接收到的信号估计信道并重新排列多个数据流。 此外,从重新布置的数据流中选择多个替代矢量,并且计算与每个替代矢量对应的度量。 此外,根据针对每个替代矢量计算的度量来计算阈值,并且从与每个替代矢量对应的度量和阈值计算发送信号的每个比特的软值。

    Viterbi decoder and method thereof
    9.
    发明授权
    Viterbi decoder and method thereof 有权
    维特比解码器及其方法

    公开(公告)号:US08055986B2

    公开(公告)日:2011-11-08

    申请号:US12064175

    申请日:2005-12-05

    IPC分类号: H03M13/03

    摘要: The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method.

    摘要翻译: 本发明涉及一种用于尾部卷积码的解码器及其方法。 解码器从信道中以卷积编码方式接收编码比特序列,生成扩展编码比特序列,维特比解码扩展编码比特序列,并产生解码数据。 此外,解码器选择解码数据的中央位序列,重新排列中央位序列,并生成最终解码数据。 因此,解码器具有用于解码以尾巴卷积编码方法编码的比特序列的简化配置,并且解码器还对以零尾卷积编码方式编码的比特序列进行解码。

    Viterbi decoder and viterbi decoding method
    10.
    发明授权
    Viterbi decoder and viterbi decoding method 有权
    维特比解码器和维特比解码方法

    公开(公告)号:US07765459B2

    公开(公告)日:2010-07-27

    申请号:US11529412

    申请日:2006-09-28

    IPC分类号: H03M13/03

    CPC分类号: H03M13/41

    摘要: The present invention relates to a Viterbi decoder and a Viterbi decoding method in a register exchange method. The Viterbi decoder receives an encoded bit sequence of a convolutional encoding method from a channel, generates an expanded encoded bit sequence by cyclically adding a part of the encoded bit sequence or the entire encoded bit sequence to the encoded bit sequence more than one time, performs a Viterbi decoding operation in a register exchange method, and generates decoded data. In addition, the Viterbi decoder selects an end bit sequence corresponding to the number of the unit of encoded bits among the decoded data, rearranges an order of the end bit sequence, and generates final decoded data.

    摘要翻译: 维特比解码器和维特比译码方法技术领域本发明涉及维特比译码器和维特比译码方法。 维特比解码器从信道接收卷积编码方法的编码比特序列,通过将编码的比特序列的一部分或整个编码的比特序列循环地添加到编码比特序列多于一次来生成扩展编码比特序列,执行 在寄存器交换方法中进行维特比解码操作,并生成解码数据。 此外,维特比解码器选择与解码数据中的编码比特数单位对应的结束比特序列,重新排列结束比特序列的顺序,并生成最终解码数据。