公开(公告)号：US06191481B1

公开(公告)日：2001-02-20

申请号：US09215099

申请日：1998-12-18

申请人： Subhas Bothra ,  Stephen L. Skala ,  Dipu Pramanik

发明人： Subhas Bothra ,  Stephen L. Skala ,  Dipu Pramanik

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor integrated circuit device having a plurality of metallization levels of patterned metallization lines that are resistant to electromigration voiding, and methods for making the electromigration void resistant metallization lines. The semiconductor integrated circuit device includes a metallization line having a first end and a second end. Oxide feature regions are defined in the metallization line, and the oxide feature regions are arranged along the metallization line between the first end and the second end. Each one of the oxide feature regions are configured to be separated from a previous oxide feature region by about a Blech length or less, and each of the oxide feature regions are configured to define a region of increased metallization atom concentration and a corresponding increased back-flow force. The oxide feature regions therefore define a composite metallization interconnect line, which is well configured to retard electromigration voiding.

摘要翻译： 本发明公开了一种半导体集成电路器件，其具有耐电迁移排空的图案化金属化线的多个金属化水平，以及用于制造电迁移空隙的金属化线的方法。 半导体集成电路器件包括具有第一端和第二端的金属化线。 氧化物特征区域被限定在金属化线中，并且氧化物特征区域沿着第一端和第二端之间的金属化线布置。 氧化物特征区域中的每一个被配置为与先前的氧化物特征区域分开大约Blech长度或更小，并且每个氧化物特征区域被配置为限定增加的金属化原子浓度的区域和相应的增加的反向 流动力。 因此，氧化物特征区域限定复合金属化互连线，其良好构造以延迟电迁移排空。

公开(公告)号：US6020647A

公开(公告)日：2000-02-01

申请号：US215902

申请日：1998-12-18

申请人： Stephen L. Skala ,  Subhas Bothra ,  Dipu Pramanik ,  William Kuang-Hua Shu

发明人： Stephen L. Skala ,  Subhas Bothra ,  Dipu Pramanik ,  William Kuang-Hua Shu

IPC分类号： H01L23/485 ,  H01L29/41

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/4943 ,  H01L2224/85201 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14

摘要： Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads. The portions of the plurality of patterned features are composite metallization regions that have a plurality of deformation preventing oxide patterns that are resistant to compression force induced plastic deformation that occurs when the plurality of gold bonding wires are applied.

摘要翻译： 公开了一种用于制造具有策略性地放置的复合金属化的半导体芯片的半导体芯片和方法。 半导体芯片包括最顶层金属化层，其限定多个图案化特征，包括用于接收相关联的多个金键合线的多个输入/输出金属化焊盘。 定义在最上层金属化层下面的金属间氧化物层。 该半导体芯片还包括下面的金属化层，其定义在金属间氧化物层之下，以将最上面的金属化层与下面的金属化层电隔离。 底层金属化具有多个图案化特征，并且多个图案化特征的部分至少部分地位于多个输入/输出金属化焊盘下方的位置。 多个图案化部分的部分是复合金属化区域，其具有多个防止变形的氧化物图案，其耐受在施加多个金焊丝时发生的压缩力引起的塑性变形。