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    Low power cache architecture
    1.
    发明授权
    Low power cache architecture 有权

    公开(公告)号：US07136984B2

    公开(公告)日：2006-11-14

    申请号：US11000054

    申请日：2004-12-01

    申请人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    发明人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

    摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

    Low power cache architecture
    2.
    发明申请
    Low power cache architecture 有权
    低功耗缓存架构

    公开(公告)号：US20050097277A1

    公开(公告)日：2005-05-05

    申请号：US11000054

    申请日：2004-12-01

    申请人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    发明人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

    摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

    摘要翻译： 在处理器高速缓存中，高速缓存电路被映射到一个或多个逻辑模块中。 响应于由高速缓存处理的微指令，每个模块可以独立于其它模块被关闭。 功率控制可以在微指令的基础上应用。 因为微指令决定了哪些模块被使用，所以可以通过关闭那些未使用的模块来实现功率节省。 可以修改高速缓存布局组织以在可寻址缓存组中分布有限数量的方式。 通过将小于总数量的方式与银行相关联（例如，一种或两种方式），可以减少银行内的存储器簇的大小。 存储器簇的这种尺寸的减小有助于减少地址解码器对存储体内的集合进行寻址所需的功率。

    Cache dynamically configured for simultaneous accesses by multiple computing engines
    4.
    发明授权
    Cache dynamically configured for simultaneous accesses by multiple computing engines 有权
    缓存动态配置为同时访问多个计算引擎

    公开(公告)号：US06665775B1

    公开(公告)日：2003-12-16

    申请号：US09667688

    申请日：2000-09-22

    申请人： Subramaniam Maiyuran ,  Salvador Palanca

    发明人： Subramaniam Maiyuran ,  Salvador Palanca

    IPC分类号： G06F1208

    CPC分类号： G06F12/0848 ,  G06F12/084 ,  G06F12/0846

    摘要： A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.

    摘要翻译： 缓存具有单个移植单元的阵列，并且可由多个计算引擎同时动态访问。 在另一实施例中，高速缓存还具有包括第一地址输入，第二地址输入和共享模式输入的标签阵列，以及电耦合到标签阵列的数据阵列，并且包括第一地址输入，第二地址输入 ，和共享模式输入。