公开(公告)号：US20070124543A1

公开(公告)日：2007-05-31

申请号：US11287949

申请日：2005-11-28

Applicant: Sudhir Dhawan ,  James Nicholson

Inventor： Sudhir Dhawan ,  James Nicholson

IPC: G06F13/28

CPC classification number: G06F12/0811 ,  G06F12/0815

Abstract: An apparatus, system, and method are disclosed for externally invalidating an uncertain cache line. In one embodiment, a monitor module monitors a processor module bus. A detection module detects a processor module evicting a cache line from a cache module. The cache line may be in an uncertain state. An invalidation module invalidates the cache line with an invalidation command directed to the processor module. In one embodiment, an update module updates a cache directory external to the processor module. The apparatus, system, and method increase memory and processor bandwidth by eliminating the need to snoop the processor module bus for evicted cache lines.

Abstract translation: 公开了用于使不确定的高速缓存行外部无效的装置，系统和方法。 在一个实施例中，监视器模块监视处理器模块总线。 检测模块检测从缓存模块中驱逐高速缓存行的处理器模块。 高速缓存线可能处于不确定状态。 无效模块使用指向处理器模块的无效命令使缓存行无效。 在一个实施例中，更新模块更新处理器模块外部的高速缓存目录。 该装置，系统和方法通过消除对被驱逐的高速缓存线窥探处理器模块总线的需要来增加存储器和处理器带宽。

公开(公告)号：US06295591B1

公开(公告)日：2001-09-25

申请号：US09281084

申请日：1999-03-30

Applicant: Richard Bealkowski ,  Scott Douglas Clark ,  Sudhir Dhawan ,  Robert Allen Drehmel

Inventor： Richard Bealkowski ,  Scott Douglas Clark ,  Sudhir Dhawan ,  Robert Allen Drehmel

IPC: G06F1200

CPC classification number: G11C29/74

Abstract: A method of providing maintenance for a memory device of a computer system without interrupting operation of the computer system, by partially mirroring a primary memory array in a secondary memory array, wherein the secondary memory array has a different amount of available memory than the primary memory array. Values are copied from the primary memory array to the permanent storage device, allowing the primary memory array to quiesce and be serviced while using the secondary memory array to operate the computer system. Thereafter, the primary memory array is brought on-line, and the mirrored values are written back from the secondary memory array to the primary memory array. The memory service program itself may be embedded in the operating system. In an illustrative embodiment, the primary memory array is located on a first removable memory card, and the secondary memory array is located on a second removable memory card. The amount of memory available in the secondary memory array may be programmable.

Abstract translation: 一种通过部分地镜像辅助存储器阵列中的主存储器阵列来为计算机系统的存储器件提供维护而不中断计算机系统的操作的方法，其中辅助存储器阵列具有与主存储器不同的可用存储器量 数组。 值从主存储器阵列复制到永久存储设备，允许主存储器阵列静止并被服务，同时使用辅助存储器阵列来操作计算机系统。 此后，主存储器阵列被联机，并且镜像值从副存储器阵列写回主存储器阵列。 存储器服务程序本身可以嵌入在操作系统中。 在说明性实施例中，主存储器阵列位于第一可移动存储卡上，并且辅助存储器阵列位于第二可移动存储卡上。 辅助存储器阵列中可用的存储器量可以是可编程的。

公开(公告)号：US5491811A

公开(公告)日：1996-02-13

申请号：US871322

申请日：1992-04-20

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  David W. Siegel

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0859

Abstract: Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.

Abstract translation: 在与高速缓存结合操作的系统存储器的上下文中提高数据传送速率的装置和方法。 在一种形式中，掩码位寄存器中的掩码位与高速缓存的字节相关联。 写入高速缓存中的相应字节时，掩码位被改变。 掩码位用于重新排序的操作序列，以便在写入高速缓存之后选择性地将数据从系统存储器写入高速缓存。 数据传输性能得到显着改善，因为当数据传输到高速缓存中时，掩码位指示高速缓存（通常为高速缓存行）的整个单元已被写入时，可以完全消除从系统存储器到高速缓存的数据选择性写入 。

公开(公告)号：US5274784A

公开(公告)日：1993-12-28

申请号：US791468

申请日：1991-11-13

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/4217

Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

Abstract translation: 在高速数据传输期间，计算机系统可以在总线地址线上的主子系统和从属子系统之间传送数据以及总线数据线。 数据在高速传输期间通过与正常总线时钟信号分离的高速时钟信号来计时。 数据以主子系统和从属子系统可以处理的最大速率传输。

公开(公告)号：US5237676A

公开(公告)日：1993-08-17

申请号：US297773

申请日：1989-01-13

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  George A. Lerom ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  George A. Lerom ,  James O. Nicholson ,  David W. Siegel

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/4217 ,  G06F13/28

Abstract: A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：US07251185B2

公开(公告)日：2007-07-31

申请号：US11064741

申请日：2005-02-24

Applicant: John M. Borkenhagen ,  Sudhir Dhawan ,  Philip R. Hillier, III ,  Joseph A. Kirscht ,  Randolph S. Kolvick

Inventor： John M. Borkenhagen ,  Sudhir Dhawan ,  Philip R. Hillier, III ,  Joseph A. Kirscht ,  Randolph S. Kolvick

IPC: G11C8/00

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F12/0607

Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种用于使用存储器的方法。 该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分 被替换 和（2）将数据存储在总存储器中。 提供了许多其他方面。

公开(公告)号：US20060187739A1

公开(公告)日：2006-08-24

申请号：US11064741

申请日：2005-02-24

Applicant: John Borkenhagen ,  Sudhir Dhawan ,  Philip Hillier ,  Joseph Kirscht ,  Randolph Kolvick

Inventor： John Borkenhagen ,  Sudhir Dhawan ,  Philip Hillier ,  Joseph Kirscht ,  Randolph Kolvick

IPC: G11C8/00

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F12/0607

Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种使用存储器的方法。 该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分 被替换 和（2）将数据存储在总存储器中。 提供了许多其他方面。

公开(公告)号：US06378027B1

公开(公告)日：2002-04-23

申请号：US09281080

申请日：1999-03-30

Applicant: Richard Bealkowski ,  Sudhir Dhawan ,  Kenneth Claude Hinz ,  Peter Matthew Thomsen

Inventor： Richard Bealkowski ,  Sudhir Dhawan ,  Kenneth Claude Hinz ,  Peter Matthew Thomsen

IPC: G06F1300

CPC classification number: G06F13/4072

Abstract: A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.

Abstract translation: 一种维护计算机系统的处理器阵列的方法，该方法是通过静止被选择进行维护的处理器，并从计算机的操作系统使用的处理器池中移除所选择的处理器。 然后，将所选择的处理器断电，同时维持处理器阵列中其他处理器的电源和操作。 所选择的处理器可能被识别为有缺陷的，或者可能被选择用于升级。 处理器阵列可以包括几个处理器集群，使得停顿，去除和掉电步骤适用于一个处理集群中的所有处理器。 操作系统将处理器阵列中的一个处理器分配为服务处理器，并且如果服务处理器是被选择用于维护的处理器，则OS将服务处理器功能重新分配给处理器阵列中的另一个处理器。

公开(公告)号：US5287482A

公开(公告)日：1994-02-15

申请号：US912043

申请日：1992-07-09

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/084

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.

Abstract translation: 用于连接到输入/输出总线的输入/输出设备的缓存。 通过输入/输出设备访问系统内存的请求通过缓存。 输入/输出设备使用的虚拟内存地址将转换为系统内存中的实际地址。 可以对虚拟内存进行分区，一些虚拟地址映射到连接到输入/输出总线的第二个内存。

公开(公告)号：US20090177946A1

公开(公告)日：2009-07-09

申请号：US11969449

申请日：2008-01-04

Applicant: Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

Inventor： Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G06F11/1044 ,  G11C2029/0411

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract translation: 一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。 存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。 奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。 奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。 在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。 在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。