公开(公告)号：US06484298B1

公开(公告)日：2002-11-19

申请号：US09574641

申请日：2000-05-18

申请人： Sudip K. Nag ,  Kamal Chaudhary ,  Jason H. Anderson ,  Madabhushi V. R. Chari ,  Sandor S. Kalman

发明人： Sudip K. Nag ,  Kamal Chaudhary ,  Jason H. Anderson ,  Madabhushi V. R. Chari ,  Sandor S. Kalman

IPC分类号： G06F1750

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.

摘要翻译： 一种用于电路设计的自动定时驱动实现的方法和装置。 在一个实施例中，使用在每次迭代中自动和动态生成的时序约束来迭代地执行实现电路设计的不同阶段。 该过程有助于确定并实现实施设计的最高性能水平。 在另一个实施例中，使用所选数量的关键连接来动态地改变时序约束。 通常，从电路设计中自动选择多个连接，并用于导出将在下一次迭代中应用的新的时序约束。 与设计中的路径相关联的松弛值也用于推导新的时序约束。

公开(公告)号：US06415425B1

公开(公告)日：2002-07-02

申请号：US09262727

申请日：1999-03-04

申请人： Kamal Chaudhary ,  Sudip K. Nag

发明人： Kamal Chaudhary ,  Sudip K. Nag

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： A method for analytical placement of cells using density surface representations. The placement of the cells is characterized as density surface fun which is two-dimensional and continuous. The cells are iteratively moved from areas having higher densities of placed cells to areas having lower densities of placed cells using the density surface function.

摘要翻译： 使用密度表面表示法分析细胞的方法。 细胞的放置被表征为二维和连续的密度表面乐趣。 使用密度表面函数将细胞从具有较高密度的放置细胞的区域迭代地移动到具有较低密度的置换细胞的区域。

公开(公告)号：US07072815B1

公开(公告)日：2006-07-04

申请号：US10213775

申请日：2002-08-06

申请人： Kamal Chaudhary ,  Krishnan Anandh ,  Sudip K. Nag ,  Guenter Stenz

发明人： Kamal Chaudhary ,  Krishnan Anandh ,  Sudip K. Nag ,  Guenter Stenz

IPC分类号： G06F9/455

CPC分类号： G06F17/5072

摘要： Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.

摘要翻译： 描述了用于连接资源的放置后优化的方法和装置。 为了优化资源放置，响应于驱动程序和加载组件以及驱动程序和加载组件之间的连接生成搜索窗口。 可以使用在直线路径搜索窗口中添加旁路资源被重新定位的替代方案。 使用基于连接的优化与基于驱动程序和资源的优化结合可以改善优化，对运行时的影响可以忽略不计。

公开(公告)号：US6086631A

公开(公告)日：2000-07-11

申请号：US57360

申请日：1998-04-08

申请人： Kamal Chaudhary ,  Sudip K. Nag

发明人： Kamal Chaudhary ,  Sudip K. Nag

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-dimensional positional relationship between the cores of the infeasible placement solution in two separate one-dimensional (i.e., horizontal and vertical) directions. Next, the constraint graphs are analyzed to determine whether they include a feasible solution (i.e., whether the overlaps existing in the placement solution can be removed simply by reallocating available resources to the overlapping cores). If one of the constraint graphs is not feasible, then the infeasible constraint graph is revised, and then the feasibility of both graphs is re-analyzed for feasibility. The feasibility analysis and constraint graph revision steps are repeated until both constraint graphs are feasible. After feasibility is determined, a slack allocation process is performed during which resources are allocated to the cores to generate a revised placement solution such that the cores are positioned as close to the original optimal solution as possible with no overlaps. Finally, the individual logic portions are re-placed using bipartite matching to complete the revised placement solution.

摘要翻译： 一种用于基于核心的可编程逻辑器件编程方法的后置放置残留重叠去除过程，当最佳布局解决方案包括一个或多个重叠核时称为。 水平和垂直约束图被用于在两个单独的一维（即，水平和垂直）方向上数学地定义不可行放置解的核心之间的二维位置关系。 接下来，分析约束图以确定它们是否包括可行的解决方案（即，是否可以通过将可用资源重新分配给重叠的核心来简单地移除存在于放置解决方案中的重叠）。 如果其中一个约束图是不可行的，则修改不可行的约束图，然后重新分析两个图的可行性。 重复可行性分析和约束图修正步骤，直到两个约束图都可行。 在确定可行性之后，执行松弛分配过程，在该过程中将资源分配给核以产生经修改的放置解决方案，使得核在不重叠的情况下尽可能靠近原始最优解定位。 最后，使用二分配匹配重新放置单个逻辑部分，以完成修订的布局解决方案。

公开(公告)号：US08593176B2

公开(公告)日：2013-11-26

申请号：US13350342

申请日：2012-01-13

申请人： Raymond Nijssen ,  Kamal Chaudhary ,  Rajit Manohar ,  Christopher LaFrieda ,  Clinton W. Kelly ,  Virantha Ekanayake

发明人： Raymond Nijssen ,  Kamal Chaudhary ,  Rajit Manohar ,  Christopher LaFrieda ,  Clinton W. Kelly ,  Virantha Ekanayake

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H03K19/0966

摘要： Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

摘要翻译： 提供了包括异步线性管线和单相管线的电路，以及形成异步线性管线电路并将其转换为单相管线电路的方法。 公开了附加电路，系统和方法。

公开(公告)号：US08146041B1

公开(公告)日：2012-03-27

申请号：US13180782

申请日：2011-07-12

申请人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

发明人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

摘要翻译： 实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。 所选择的电路元件可以被转换成锁存器。 在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。 当电路设计的时序改善时，计算机可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。 可以输出电路设计。

公开(公告)号：US07590960B1

公开(公告)日：2009-09-15

申请号：US11787925

申请日：2007-04-18

申请人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

发明人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5072

摘要： A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

摘要翻译： 将分割电路设计的电路元件放置在目标可编程逻辑器件（PLD）上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区，选择电路设计的电路元件，以及选择候选 位于目标PLD的逻辑边界内。 该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。 所选择的电路元件可以根据验证选择性地放置在候选位置。

公开(公告)号：US07146590B1

公开(公告)日：2006-12-05

申请号：US10927734

申请日：2004-08-27

申请人： Kamal Chaudhary

发明人： Kamal Chaudhary

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

摘要翻译： 估计可编程逻辑器件的拥塞的方法可以包括为可编程逻辑器件中的每个资源计算多个扇入路径，并为可编程逻辑器件中的每个资源计算多个扇出路径。 对于可编程逻辑器件的每个资源，可以确定具有不同路径特性的多个路径，并且可以分配概率。 可以根据确定步骤计算拥塞的一个或多个措施。

公开(公告)号：US20120112792A1

公开(公告)日：2012-05-10

申请号：US13350342

申请日：2012-01-13

申请人： Raymond Nijssen ,  Kamal Chaudhary ,  Rajit Manohar ,  Christopher LaFrieda ,  Clinton W. Kelly ,  Virantha Ekanayake

发明人： Raymond Nijssen ,  Kamal Chaudhary ,  Rajit Manohar ,  Christopher LaFrieda ,  Clinton W. Kelly ,  Virantha Ekanayake

IPC分类号： H03K19/00

CPC分类号： H03K19/0966

摘要： Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

摘要翻译： 提供了包括异步线性管线和单相管线的电路，以及形成异步线性管线电路并将其转换为单相管线电路的方法。 公开了附加电路，系统和方法。

公开(公告)号：US07536661B1

公开(公告)日：2009-05-19

申请号：US11361370

申请日：2006-02-24

申请人： Amit Singh ,  Kamal Chaudhary

发明人： Amit Singh ,  Kamal Chaudhary

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.

摘要翻译： 优化目标设备的电路设计的一部分的方法可以包括在电路设计的初始放置之后从多个区域识别关键区域。 关键区域可以至少部分地由至少一个输入块和至少一个输出块来定义。 关键区域的块可以重新定位到关键区域内的不同位置。 该方法还可以包括根据成本函数评估关键区域的块的重新定位，并且继续重新定位块并评估临界区域中块的重定位，直到满足至少一个退出准则。