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公开(公告)号：US08631213B2
公开(公告)日：2014-01-14
申请号：US12883878
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
发明人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F13/1684
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US20120072678A1
公开(公告)日：2012-03-22
申请号：US12883878
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
发明人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F13/1684
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US20130054901A1
公开(公告)日：2013-02-28
申请号：US13217513
申请日：2011-08-25
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations.
摘要翻译： 存储器控制器经由可以包括多个端口的接口来接收存储器操作。 每个端口耦合到实时或非实时请求者，并且所接收的存储器操作被分类为实时或非实时的，并且在访问存储器之前存储在队列中。 在内存控制器中，排队等待的内存操作计划进行维修。 响应于检测到未完成的存储器操作的数量已经超过阈值，逻辑控制非实时存储器操作的调度。 节流与未完成记忆操作的数量成比例。
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公开(公告)号：US08301941B2
公开(公告)日：2012-10-30
申请号：US13305202
申请日：2011-11-28
CPC分类号： G01R31/31716
摘要： An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译： 设备可以包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可以由处理器编程成环回测试操作模式，并且在回送测试模式中，存储器控制器可以被配置为通过互连从处理器接收第一写入操作。 存储器控制器可以被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 存储器控制器还可以被配置为在互连上将读数据作为读数据返回，用于从互连上的处理器接收到的第一读操作。
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公开(公告)号：US20120072787A1
公开(公告)日：2012-03-22
申请号：US13305202
申请日：2011-11-28
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。
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6.发明申请Multi-Ported Memory Controller with Ports Associated with Traffic Classes 审中-公开具有与流量类相关的端口的多端口存储器控制器公开(公告)号：US20120072677A1
公开(公告)日：2012-03-22
申请号：US12883848
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/18
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US07836372B2
公开(公告)日：2010-11-16
申请号：US11760566
申请日：2007-06-08
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。
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公开(公告)号：US20080307286A1
公开(公告)日：2008-12-11
申请号：US11758322
申请日：2007-06-05
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译： 在一个实施例中，一种装置包括耦合到控制电路的检查/校正电路。 检查/校正电路被耦合以接收数据块和相应的校验位。 数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。 检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。 控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号 设备故障 K，L，M和N中的每一个是大于1的整数。
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公开(公告)号：US20080307276A1
公开(公告)日：2008-12-11
申请号：US11760566
申请日：2007-06-08
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。
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公开(公告)号：US08458406B2
公开(公告)日：2013-06-04
申请号：US12955699
申请日：2010-11-29
申请人： Sukalpa Biswas , Hao Chen , Brian P. Lilly
发明人： Sukalpa Biswas , Hao Chen , Brian P. Lilly
IPC分类号： G06F2/00
CPC分类号： G06F12/0893 , G06F13/1673
摘要： In one embodiment, a memory controller may be configured to transmit two or more critical words (or beats) corresponding to two or more different read requests prior to returning the remaining beats of the read requests. Such an embodiment may reduce latency to the sources of the memory requests, which may be stalled awaiting the critical words. The remaining words may fill a cache block or other buffer, but may not be required by the sources as quickly as the critical words in order to support higher performance. In some embodiments, once a remaining beat of a block is transmitted, all of the remaining beats may be transmitted contiguously. In other embodiments, additional critical words may be forwarded between remaining beats of a block.
摘要翻译： 在一个实施例中，存储器控制器可以被配置为在返回读取请求的剩余节拍之前发送对应于两个或更多个不同读取请求的两个或更多个关键词（或节拍）。 这样的实施例可以减少对可能被停止等待关键词的存储器请求的来源的等待时间。 剩余的单词可以填充缓存块或其他缓冲区，但可能不需要来源与关键字一样快以支持更高的性能。 在一些实施例中，一旦发送了块的剩余节拍，则所有剩余的节拍可以连续传输。 在其他实施例中，可以在块的剩余节拍之间转发附加关键词。
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