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    Method and device for converting bit rate of serial data
    3.
    发明授权
    Method and device for converting bit rate of serial data 失效
    用于转换串行数据比特率的方法和设备

    公开(公告)号：US06480512B1

    公开(公告)日：2002-11-12

    申请号：US09222682

    申请日：1998-12-29

    申请人： Young-Jin Ahn

    发明人： Young-Jin Ahn

    IPC分类号： H04J322

    CPC分类号： H04L25/05 ,  Y10S370/914

    摘要： A method and device for converting high rate serial data into low rate serial data are disclosed. The device includes: first and second clock application parts for selectively generating a high rate clock and low rate clock according to a selection signal; a first bit rate conversion part for receiving and latching the high rate serial data according to the high rate clock from the first clock application part, and for outputting the latched data at a low rate according to the low rate clock; a second bit rate conversion part for receiving and latching the high rate serial data according to the high rate clock from the second clock application part, and for outputting the latched data at a low rate according to the low rate clock; a first selector for receiving and selectively outputting the output of the first bit rate conversion part and the high rate serial data; a second selector for receiving and selectively outputting the output of the second bit rate conversion part and the high rate serial data; a selection part for controlling outputting of two input signals which are applied to the first and second selectors; and a third selector for receiving the outputs of the first and second bit rate conversion parts, and for sequentially outputting the high rate serial data in accordance with the low rate clock. A corresponding method and device for converting low rate serial data into high rate serial data are also disclosed.

    摘要翻译： 公开了一种将高速率串行数据转换为低速率串行数据的方法和装置。 该装置包括：第一和第二时钟应用部分，用于根据选择信号选择性地产生高速率时钟和低速率时钟; 第一比特率转换部分，用于根据来自第一时钟应用部分的高速率时钟接收和锁存高速率串行数据，并根据低速率时钟以低速率输出锁存数据; 第二比特率转换部分，用于根据来自第二时钟应用部分的高速率时钟接收和锁存高速率串行数据，并且根据低速率时钟以低速率输出锁存数据; 第一选择器，用于接收和选择性地输出第一比特率转换部分和高速率串行数据的输出; 第二选择器，用于接收和选择性地输出第二比特率转换部分和高速率串行数据的输出; 选择部分，用于控制施加到第一和第二选择器的两个输入信号的输出; 以及第三选择器，用于接收第一和第二比特率转换部分的输出，并且用于根据低速率时钟依次输出高速串行数据。 还公开了用于将低速率串行数据转换成高速率串行数据的相应方法和装置。