公开(公告)号：US07038266B2

公开(公告)日：2006-05-02

申请号：US10791246

申请日：2004-03-01

申请人： Sung Hsiung Wang

发明人： Sung Hsiung Wang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L21/76807

摘要： A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrate4s the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.

摘要翻译： 微电子产品及其制造方法各自提供了形成在第一介电层和形成在其上露出有第一接触区域和第二接触区域的基板上形成的第二电介质层之间的电容器。 电容器还连接到穿透第一介电层并接触第一接触区域的第一导体柱和穿过第二介电层的第二导体柱。 在双镶嵌孔内通过第二介电层和第一介电层形成连接的导体互连和导体柱层，并与第二接触区接触。 当在双镶嵌孔口内形成沟槽时采用的蚀刻停止层也钝化电容器侧壁。

公开(公告)号：US07229879B2

公开(公告)日：2007-06-12

申请号：US11286999

申请日：2005-11-22

申请人： Sung Hsiung Wang

发明人： Sung Hsiung Wang

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/55 ,  H01L21/76807

摘要： A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.

摘要翻译： 微电子产品及其制造方法各自提供了形成在第一介电层和形成在其上露出有第一接触区域和第二接触区域的基板上形成的第二电介质层之间的电容器。 电容器还连接到穿透第一介电层并接触第一接触区域的第一导体柱和穿过第二介电层的第二导体柱。 在双镶嵌孔内通过第二介电层和第一介电层形成连接的导体互连和导体柱层，并与第二接触区接触。 当在双镶嵌孔口内形成沟槽时采用的蚀刻停止层也钝化电容器侧壁。