公开(公告)号：US08174478B2

公开(公告)日：2012-05-08

申请号：US11760174

申请日：2007-06-08

申请人： Sung-Man Kim ,  Hong-Woo Lee ,  Byeong-Jae Ahn ,  Young-Geol Song ,  Bong-Jun Lee ,  Yeon-Kyu Moon ,  Kyung-Wook Kim ,  Jin-Suk Seo

发明人： Sung-Man Kim ,  Hong-Woo Lee ,  Byeong-Jae Ahn ,  Young-Geol Song ,  Bong-Jun Lee ,  Yeon-Kyu Moon ,  Kyung-Wook Kim ,  Jin-Suk Seo

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/041

摘要： A gate driving circuit and a display apparatus having the gate driving circuit include a pull-up part and a carry part pull up a present gate signal and a present carry signal, respectively, to a first clock during a first period within one frame. A pull-down part receives a next gate signal to discharge the present gate signal to a source power voltage. A pull-up driving part is connected to control terminals of the carry part and pull-up part (Q-node) to turn the carry part and pull-up part on and off. A floating preventing part prevents an output terminal of the carry part from being floated in response to the first clock during a second period within the one frame.

摘要翻译： 具有栅极驱动电路的栅极驱动电路和显示装置包括上拉部分和进位部分，分别在一帧内的第一时段期间将当前栅极信号和当前进位信号上拉到第一时钟。 下拉部分接收下一个栅极信号，以将当前栅极信号放电到源极电压。 上拉驱动部分连接到进位部分和上拉部分（Q-节点）的控制端子，以使进位部分和上拉部分打开和关闭。 浮动防止部件在一帧内的第二时段期间，响应于第一时钟防止进位部分的输出端子浮起。

公开(公告)号：US07417458B2

公开(公告)日：2008-08-26

申请号：US11840471

申请日：2007-08-17

申请人： Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

发明人： Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K17/161 ,  G09G3/3677 ,  G11C19/184

摘要： In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n−1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n−1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.

摘要翻译： 在栅极驱动电路和具有该栅极驱动电路的显示装置中，纹波防止部分连接到上拉部分和控制端子（Q-节点）以复位Q-节点。 纹波防止部包括在第（n-1）个H周期内在第一时钟的高周期期间复位Q-节点的第一纹波防止装置和在高周期期间复位Q-节点的第二纹波防止装置 （n-1）个H周期内的第二个时钟。 在前一进位节点和第二纹波防止装置之间连接防回流装置，以防止Q-节点的电荷回流到先前的进位节点。

公开(公告)号：US20080048712A1

公开(公告)日：2008-02-28

申请号：US11840471

申请日：2007-08-17

申请人： Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

发明人： Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

IPC分类号： H03K17/16

CPC分类号： H03K17/161 ,  G09G3/3677 ,  G11C19/184

摘要： In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n−1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n−1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.

摘要翻译： 在栅极驱动电路和具有该栅极驱动电路的显示装置中，纹波防止部分连接到上拉部分和控制端子（Q-节点）以复位Q-节点。 纹波防止部包括在第（n-1）个H周期内在第一时钟的高周期期间复位Q-节点的第一纹波防止装置和在高周期期间复位Q-节点的第二纹波防止装置 （n-1）个H周期内的第二个时钟。 在前一进位节点和第二纹波防止装置之间连接防回流装置，以防止Q-节点的电荷回流到先前的进位节点。

公开(公告)号：US08264443B2

公开(公告)日：2012-09-11

申请号：US12241880

申请日：2008-09-30

申请人： Hong-Woo Lee ,  Hyeon-Hwan Kim ,  Byeong-Jae Ahn ,  Sun-Hyung Kim ,  Sung-Man Kim ,  Bong-Jun Lee

发明人： Hong-Woo Lee ,  Hyeon-Hwan Kim ,  Byeong-Jae Ahn ,  Sun-Hyung Kim ,  Sung-Man Kim ,  Bong-Jun Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677

摘要： A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

摘要翻译： 门驱动电路包括级级，级联级，每级包括：在水平扫描周期（1H）期间将门电压上拉至时钟信号的上拉部分; 在水平扫描期间（1H）中将进位电压拉入时钟信号的进位部分; 上拉驱动部分连接到与进位部分和上拉部分共同的控制端子（Q-节点），并且从上一级接收先前的进位电压以接通上拉部分和进位 部分; 以及纹波防止部，其基于在所述进位部和所述上拉部的所述Q节点处产生的波纹来防止在前一级的前一Q点产生的纹波。

公开(公告)号：US20090167733A1

公开(公告)日：2009-07-02

申请号：US12332213

申请日：2008-12-10

申请人： Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

发明人： Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

IPC分类号： G09G5/00

CPC分类号： H01L27/124 ,  H01L27/1288

摘要： A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.

摘要翻译： 显示基板包括基底基板，第一线，第二线，桥接线，薄膜晶体管（TFT），存储线和像素电极。 第一线在基底基板上沿第一方向延伸。 第二线在基底基板上沿第二方向延伸，并且相对于第一线分成两部分。 桥接线与第一和第二桥接触区域中的第二线路的两个部分接触。 TFT包括与数据接触区域中的第一和第二线路之一接触的源电极。 存储线形成在第一和第二线之一上。 像素电极形成在存储线上并与TFT电连接。 显示基板减少像素电极和数据线之间的寄生电容的形成。

公开(公告)号：US08223283B2

公开(公告)日：2012-07-17

申请号：US12332213

申请日：2008-12-10

申请人： Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

发明人： Bong-Jun Lee ,  Byeong-Jae Ahn ,  Yeo-Geon Yoon ,  Hong-Woo Lee ,  Hyuk-Jin Kim ,  Jong-Oh Kim ,  Gyu-Tae Kim

IPC分类号： G02F1/1343

CPC分类号： H01L27/124 ,  H01L27/1288

摘要： A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.

摘要翻译： 显示基板包括基底基板，第一线，第二线，桥接线，薄膜晶体管（TFT），存储线和像素电极。 第一线在基底基板上沿第一方向延伸。 第二线在基底基板上沿第二方向延伸，并且相对于第一线分成两部分。 桥接线与第一和第二桥接触区域中的第二线路的两个部分接触。 TFT包括与数据接触区域中的第一和第二线路之一接触的源电极。 存储线形成在第一和第二线之一上。 像素电极形成在存储线上并与TFT电连接。 显示基板减少像素电极和数据线之间的寄生电容的形成。

公开(公告)号：US08306177B2

公开(公告)日：2012-11-06

申请号：US12575895

申请日：2009-10-08

申请人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

发明人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

摘要： A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

摘要翻译： 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

公开(公告)号：US08565370B2

公开(公告)日：2013-10-22

申请号：US13612532

申请日：2012-09-12

申请人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

发明人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

摘要： A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

摘要翻译： 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

公开(公告)号：US09396696B2

公开(公告)日：2016-07-19

申请号：US12861360

申请日：2010-08-23

申请人： Sung-Man Kim ,  Hong-Woo Lee ,  Chang-Ho Lee ,  Eung-Gyu Lee ,  Yu-Jun Kim ,  Yu-Jin Kim ,  Jin-Suk Seo ,  Byung-Su Oh

发明人： Sung-Man Kim ,  Hong-Woo Lee ,  Chang-Ho Lee ,  Eung-Gyu Lee ,  Yu-Jun Kim ,  Yu-Jin Kim ,  Jin-Suk Seo ,  Byung-Su Oh

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G5/00 ,  G09G3/36

摘要： A liquid crystal display (“LCD”) device includes a display panel, a data driving part, and at least one first light-blocking part and at least one second light-blocking part. The display panel includes a plurality of pixels and a plurality of data lines. The pixels are arranged in a column direction and a row direction. At least one of the data lines extends in a zigzag shape along the column direction to be discontinuously disposed between two adjacent columns of the pixels. The at least one data line is electrically connected to two of the pixels that are adjacent in the row direction. The second light-blocking part is thinner than the first light-blocking part. The first light-blocking part and the second light-blocking are repeatedly disposed on an area between two adjacent columns of the pixels. The data driving part applies a data signal to the data lines.

摘要翻译： 液晶显示器（“LCD”）器件包括显示面板，数据驱动部分和至少一个第一遮光部分和至少一个第二遮光部分。 显示面板包括多个像素和多条数据线。 像素沿列方向和行方向排列。 数据线中的至少一条沿着列方向以锯齿形延伸，以不连续地设置在像素的两个相邻列之间。 至少一条数据线电连接到在行方向上相邻的两个像素。 第二遮光部分比第一遮光部分薄。 第一遮光部分和第二光阻被重复地设置在像素的两个相邻列之间的区域上。 数据驱动部分将数据信号应用于数据线。

公开(公告)号：US20080043191A1

公开(公告)日：2008-02-21

申请号：US11839752

申请日：2007-08-16

申请人： Sung-Man Kim ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Yong Woo Lee ,  Hong-Woo Lee ,  Jin-Suk Seo

发明人： Sung-Man Kim ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Yong Woo Lee ,  Hong-Woo Lee ,  Jin-Suk Seo

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707

摘要： Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

摘要翻译： 公开了一种液晶显示装置，包括第一基板，第二基板和介于其间的液晶层。 第一基板上设置有栅线和数据线。 栅极线和数据线彼此交叉并且彼此绝缘。 像素电极堆叠在栅极线和数据线上。 每个像素电极包括彼此间隔开的第一和第二子像素电极和将第一子像素电极连接到第二子像素电极的连接电极。 第二基板上设置有公共电极。 公共电极包括形成在第一子像素电极的中心上的第一域分隔器和形成在第二子像素电极的中心的第二域分隔器。