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    Method and system for data transformation in a heterogeneous computer system
    1.
    发明授权
    Method and system for data transformation in a heterogeneous computer system 失效

    公开(公告)号：US07065588B2

    公开(公告)日：2006-06-20

    申请号：US09928256

    申请日：2001-08-10

    申请人： Suresh L. Konda ,  Michael Collins ,  Pranab K. Nag

    发明人： Suresh L. Konda ,  Michael Collins ,  Pranab K. Nag

    IPC分类号： G06F15/16

    CPC分类号： H04L67/2823 ,  G06F17/30569 ,  H04L67/28

    摘要： A data transformation system includes clients, which initiate requests for transformation of data between first and second data formats. The system also includes peer transformation servers having data converters and graphs of available transformations between input and output data formats of such servers. The graph includes unidirectional edges, which extend between corresponding pairs of the formats. The servers collectively include one or more converters for each of the edges. The servers receive the requests and select plural intermediate transformations from the first format to plural intermediate formats, and a final transformation from an intermediate format to the second format. Each of the intermediate and final transformations is associated with a corresponding one of the edges. The servers initiate the converters corresponding to the selected transformations, in order to obtain and dispose the data in the second format. A communication network provides communication among the client and servers.

    Static RAM memory cell using N-channel MOS transistors
    2.
    发明授权
    Static RAM memory cell using N-channel MOS transistors 失效
    使用N沟道MOS晶体管的静态RAM存储单元

    公开(公告)号：US5051951A

    公开(公告)日：1991-09-24

    申请号：US653859

    申请日：1991-02-08

    申请人： Wojciech Maly ,  Pranab K. Nag

    发明人： Wojciech Maly ,  Pranab K. Nag

    IPC分类号： G11C7/20 ,  G11C14/00

    CPC分类号： G11C14/00 ,  G11C7/20 ,  Y10S257/903

    摘要： A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

    摘要翻译： 在NMOS SRAM中利用浮栅NMOS增强型晶体管，从而降低存储单元的功耗，尺寸和电路复杂性。 允许负载晶体管的栅极浮动，而不与存储单元电路电连接。 通过栅极与源极，漏极和体半导体的电容在负载晶体管的栅极上产生偏置电压，并且电导保持在导通阈值以下。 通过调整栅极电容和根据需要使用紫外线去除电荷来建立栅极偏置。