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18 条记录 (耗时 0.027 秒)

    Image coder/decoder, image coding/decoding method, and storage medium
    1.
    发明授权
    Image coder/decoder, image coding/decoding method, and storage medium 失效
    图像编码器/解码器，图像编码/解码方法和存储介质

    公开(公告)号：US07218788B2

    公开(公告)日：2007-05-15

    申请号：US10073112

    申请日：2002-02-12

    申请人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Satoh ,  Yukio Chiba ,  Katsumi Otsuka

    发明人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Satoh ,  Yukio Chiba ,  Katsumi Otsuka

    IPC分类号： G06K9/36 ,  G06K9/46

    CPC分类号： G06T9/007

    摘要： In image data coding and decoding processing, in order to improve efficiency by processing a plurality of factors in one cycle as long as possible, the factors are rearranged, in coding or decoding processing, in a predetermined scan sequence such that significant factors and 0s are paired. In addition, an appropriate scan sequence is selected in accordance with the distribution state of frequencies to further improve the efficiency.

    摘要翻译： 在图像数据编码和解码处理中，为了通过在一个周期内尽可能多地处理多个因素来提高效率，因此在编码或解码处理中以预定的扫描序列重新排列这些因素，使得重要因素和0是 配对 此外，根据频率的分布状态选择适当的扫描序列，以进一步提高效率。

    Image processing method, apparatus, and storage medium
    2.
    发明授权
    Image processing method, apparatus, and storage medium 有权
    图像处理方法，装置和存储介质

    公开(公告)号：US06947602B2

    公开(公告)日：2005-09-20

    申请号：US10021247

    申请日：2001-12-19

    申请人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Satoh ,  Yukio Chiba ,  Katsumi Otsuka

    发明人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Satoh ,  Yukio Chiba ,  Katsumi Otsuka

    IPC分类号： H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  G06K9/36

    CPC分类号： H04N19/423 ,  H04N19/60 ,  H04N19/61

    摘要： Whether a header information processor quickly enters a program inactive state at the timing when it issues an operation start command of an encoding process for a predetermined processing unit to a variable-length code encoder, or the header information processor enters the program inactive state upon completion of execution steps to be processed is adaptively selected in accordance with the number of execution steps. One memory is shared by the header information processor and variable-length code encoder, and address input permission means for controlling to grant permission of an address input to the memory to one of the header information processor and the variable-length code encoder is provided. The memory is used as a work area of the header information processor, and as a storage area of a variable-length code table which is looked up by the variable-length code encoder.

    摘要翻译： 在向可变长度码编码器发出预定处理单元的编码处理的操作开始命令的定时，头信息处理器是否快速进入程序无效状态，或者头信息处理器在完成时进入程序无效状态 根据执行步骤的数量自适应地选择要处理的执行步骤。 一个存储器由标题信息处理器和可变长度代码编码器共享，并且提供地址输入许可装置，用于控制将对存储器输入的地址的许可授予标题信息处理器和可变长度代码编码器之一。 存储器用作标题信息处理器的工作区域，并且作为可变长度代码编码器查找的可变长度代码表的存储区域。

    Decoding apparatus, method, and storage medium for inputting and decoding variable-length coded data
    4.
    发明授权
    Decoding apparatus, method, and storage medium for inputting and decoding variable-length coded data 失效
    用于输入和解码可变长度编码数据的解码装置，方法和存储介质

    公开(公告)号：US06993202B2

    公开(公告)日：2006-01-31

    申请号：US10082280

    申请日：2002-02-26

    申请人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Sato ,  Yukio Chiba ,  Katsumi Otsuka

    发明人： Susumu Igarashi ,  Tetsuya Tateno ,  Makoto Sato ,  Yukio Chiba ,  Katsumi Otsuka

    IPC分类号： G06K9/36 ,  G06K9/46

    CPC分类号： H03M7/42 ,  H04N19/13 ,  H04N19/60 ,  H04N19/61

    摘要： A decoding apparatus has: M tables for storing, in correspondence with M types of variable-length code tables, minimum code words or maximum code words of classes of variable-length code words constructing a variable-length code table; a table selector which selects one table from the M tables; N comparators which compare input coded data with the minimum code words or maximum code words outputted from the table selected by the table selector; a switch circuit and a priority encoder which obtain a class number corresponding to an initial code word of the input coded data based on results of comparison by the N comparators; a code length converter which converts the class number into a code length; and an address generator which generates an address to access a memory holding decoded data from the class number and the code length outputted said code length converter. The data outputted from the memory based on the address becomes decoded data of the input coded data.

    摘要翻译： 解码装置具有：M表，用于存储与M类型的可变长度代码表相对应的最小代码字或构成可变长度代码表的可变长度代码字的类别的最大代码字; 表选择器，从M表中选择一个表; N个比较器，其将输入编码数据与从表选择器选择的表输出的最小码字或最大码字进行比较; 基于所述N个比较器的比较结果，获得与所述输入编码数据的初始码字对应的类号的开关电路和优先编码器; 将类号转换为码长的码长转换器; 以及地址发生器，其生成地址以访问存储来自类号码的解码数据的存储器和输出所述码长转换器的码长度。 基于地址从存储器输出的数据成为输入编码数据的解码数据。

    Decoding apparatus and method therefor
    6.
    发明授权
    Decoding apparatus and method therefor 失效
    解码装置及其方法

    公开(公告)号：US5751233A

    公开(公告)日：1998-05-12

    申请号：US644246

    申请日：1996-05-10

    申请人： Tetsuya Tateno ,  Yuji Minami

    发明人： Tetsuya Tateno ,  Yuji Minami

    IPC分类号： G06T9/00 ,  H03M7/42 ,  H03M7/44 ,  H04N1/419 ,  H03M7/40

    CPC分类号： G06T9/005 ,  H03M7/425 ,  H04N1/419 ,  H04N19/13 ,  H04N19/91

    摘要： A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.

    摘要翻译： 解码器对诸如Modified Huffman，Modified READ和Modified Modified READ码的输入代码进行解码，并且包括检测输入代码的连续前导零位数的零位检测器。 地址压缩器通过执行表示检测到的零比特数的数据和除了连续前导零比特和数据的下一个比特之外的数据的逻辑运算来形成地址数据。 通过来自地址压缩器的形成的地址数据来解决用于代码转换的参考表，并且输出与输入代码对应的解码数据。

    Relay apparatus for relaying communication from CPU to peripheral device
    10.
    发明授权
    Relay apparatus for relaying communication from CPU to peripheral device 失效
    用于中继从CPU到外围设备的通信的中继装置

    公开(公告)号：US07328288B2

    公开(公告)日：2008-02-05

    申请号：US11003294

    申请日：2004-12-03

    申请人： Tetsuya Tateno

    发明人： Tetsuya Tateno

    IPC分类号： G06F13/00 ,  G06F3/00

    CPC分类号： G06F13/4291

    摘要： In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information required for communication with the peripheral devices inside the relay apparatus; and command holding sections, which are provided adjacent to the communication information holding section, for holding commands used to communicate desired information inside the communication information holding section to the peripheral device. The CPU writes desired information in the communication information holding section and the command holding section inside the relay apparatus by burst-mode communication, and the relay apparatus performs communication with the peripheral devices in accordance with instructions from the command holding section after the writing of the desired information in the communication holding section and the command holding section is completed.

    摘要翻译： 为了降低CPU的开销，用于将从CPU通信到外围设备的中继装置包括通信信息保持部分，用于保持与中继设备内的外围设备通信所需的信息; 以及与通信信息保持部相邻设置的命令保持部，用于保持用于在通信信息保持部内通信期望信息到外围设备的命令。 CPU通过突发模式通信在通信信息保持部分和中继装置内部的命令保持部分中写入所需信息，并且中继装置在写入之后根据来自命令保持部分的指令与外围设备进行通信 通信保持部和命令保持部中的期望信息完成。