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    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory
    2.
    发明申请
    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory 审中-公开
    具有由具有分布式片上共享存储器和外部共享存储器的片上网络链接的可编程处理元件阵列的片上系统

    公开(公告)号：US20100191911A1

    公开(公告)日：2010-07-29

    申请号：US12639325

    申请日：2009-12-16

    申请人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    发明人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    IPC分类号： G06F15/80 ,  G06F9/06 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F15/16

    摘要： An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

    摘要翻译： 具有可编程处理元件阵列的集成电路和由片上通信网络链接的存储器接口。 每个处理元件包括多个处理核心和本地存储器。 存储器接口块可操作地耦合到外部存储器和片上通信网络。 存储器接口支持通过片上通信网络响应于从阵列的处理元件传送的消息来访问外部存储器。 阵列的多个处理元件的一部分本地存储器的一部分以及外部存储器的一部分都被分配以在执行分配在其上的编程操作期间存储由阵列的多个处理元件共享的数据。

    System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween
    3.
    发明申请
    System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween 审中-公开
    系统级芯片采用利用接收侧流控制的节点网络对于其间通信的消息

    公开(公告)号：US20100191814A1

    公开(公告)日：2010-07-29

    申请号：US12639326

    申请日：2009-12-16

    申请人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Michael Singngee Yeo

    发明人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Michael Singngee Yeo

    IPC分类号： G06F15/16

    CPC分类号： G06F15/16

    摘要： An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node. In the preferred embodiment, the transmitter node is adapted to initiate transmission of a message to the receiver node only if the total number of credits maintained at the transmitter node is sufficient to store the message at the receiver node. A given credit can include an address generated by a receiver node and representing an address in the local memory of the receiver node for storing data. The transmitter node transmits the address of the given credit to the receiver node for storing data therein.

    摘要翻译： 集成电路，由片上通信网络链接的节点阵列。 使用表示相关节点处的硬件资源的逻辑信道在节点之间传送消息。 给定的逻辑信道与接收机节点和发射机节点相关联。 接收机节点适于向发射机节点发送流量控制消息。 流控制消息包括识别接收机节点的硬件资源的信用，该硬件资源可用于通过给定逻辑信道接收消息。 发射机节点适于维持作为从接收机节点传送的流控制消息的一部分包括的信用的运行总计，并且根据在发射机节点处保持的信用的运行总计来发起消息到接收机节点的传输。 在优选实施例中，只有在发射机节点处保存的信用总数足以在接收机节点处存储消息时，发射机节点适于发起消息到接收机节点的传输。 给定的信用可以包括由接收器节点生成的地址并且表示用于存储数据的接收器节点的本地存储器中的地址。 发射机节点将给定信用的地址发送到接收机节点，用于在其中存储数据。

    System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes
    4.
    发明申请
    System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes 审中-公开
    系统级芯片支持可配置对称多处理节点的网络阵列

    公开(公告)号：US20100161938A1

    公开(公告)日：2010-06-24

    申请号：US12342660

    申请日：2008-12-23

    申请人： Marco Heddes ,  Massimo Ravasi

    发明人： Marco Heddes ,  Massimo Ravasi

    IPC分类号： G06F15/76 ,  G06F9/02

    CPC分类号： G06F15/16

    摘要： An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means assigns threads to the processing cores of the given processing element in a configurable manner. The configuration of the thread scheduling means defines one or more logical symmetric multiprocessors for executing threads on the given processing element. A logical symmetric multiprocessor is realized by a defined set of processing cores assigned to a group of threads executing on the given processing element.

    摘要翻译： 一种具有由片上通信网络链接的可编程处理元件阵列的集成电路。 每个处理元件包括多个处理核心，本地存储器和用于调度给定处理元件的处理核上的线程执行的线程调度装置。 线程调度装置以可配置的方式将线程分配给给定处理元件的处理核心。 线程调度装置的配置定义了用于在给定处理元件上执行线程的一个或多个逻辑对称多处理器。 逻辑对称多处理器由分配给在给定处理元件上执行的一组线程的一组定义的处理核实现。