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1.发明申请System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory 审中-公开具有由具有分布式片上共享存储器和外部共享存储器的片上网络链接的可编程处理元件阵列的片上系统公开(公告)号：US20100191911A1
公开(公告)日：2010-07-29
申请号：US12639325
申请日：2009-12-16
CPC分类号： G06F15/16
摘要： An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.
摘要翻译： 具有可编程处理元件阵列的集成电路和由片上通信网络链接的存储器接口。 每个处理元件包括多个处理核心和本地存储器。 存储器接口块可操作地耦合到外部存储器和片上通信网络。 存储器接口支持通过片上通信网络响应于从阵列的处理元件传送的消息来访问外部存储器。 阵列的多个处理元件的一部分本地存储器的一部分以及外部存储器的一部分都被分配以在执行分配在其上的编程操作期间存储由阵列的多个处理元件共享的数据。
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2.发明申请System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween 审中-公开系统级芯片采用利用接收侧流控制的节点网络对于其间通信的消息公开(公告)号：US20100191814A1
公开(公告)日：2010-07-29
申请号：US12639326
申请日：2009-12-16
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node. In the preferred embodiment, the transmitter node is adapted to initiate transmission of a message to the receiver node only if the total number of credits maintained at the transmitter node is sufficient to store the message at the receiver node. A given credit can include an address generated by a receiver node and representing an address in the local memory of the receiver node for storing data. The transmitter node transmits the address of the given credit to the receiver node for storing data therein.
摘要翻译： 集成电路，由片上通信网络链接的节点阵列。 使用表示相关节点处的硬件资源的逻辑信道在节点之间传送消息。 给定的逻辑信道与接收机节点和发射机节点相关联。 接收机节点适于向发射机节点发送流量控制消息。 流控制消息包括识别接收机节点的硬件资源的信用，该硬件资源可用于通过给定逻辑信道接收消息。 发射机节点适于维持作为从接收机节点传送的流控制消息的一部分包括的信用的运行总计，并且根据在发射机节点处保持的信用的运行总计来发起消息到接收机节点的传输。 在优选实施例中，只有在发射机节点处保存的信用总数足以在接收机节点处存储消息时，发射机节点适于发起消息到接收机节点的传输。 给定的信用可以包括由接收器节点生成的地址并且表示用于存储数据的接收器节点的本地存储器中的地址。 发射机节点将给定信用的地址发送到接收机节点，用于在其中存储数据。
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3.发明授权Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) 有权在SONET（同步光网络）虚级联（VCAT）中组合硬件和软件实现链路容量调整方案（LCAS）公开(公告)号：US07558287B2
公开(公告)日：2009-07-07
申请号：US11210135
申请日：2005-08-23
CPC分类号： H04J3/1611
摘要： Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
摘要翻译： 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。
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公开(公告)号：US07672315B2
公开(公告)日：2010-03-02
申请号：US11210127
申请日：2005-08-23
IPC分类号： H04L12/56
CPC分类号： H04J3/0623 , H04J3/1611 , H04J2203/0094
摘要： Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
摘要翻译： 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。
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