公开(公告)号：US10831956B2

公开(公告)日：2020-11-10

申请号：US15827202

申请日：2017-11-30

Applicant: Synopsys, Inc.

Inventor： Eduard Cerny ,  Gerald Taylor

IPC: G06F30/33 ,  G06F30/23 ,  G06F30/30 ,  G06F30/17 ,  G06F30/333 ,  G06F119/18

Abstract: A system receive as input a circuit design and a description of the behavior of the circuit design specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. The system generates an alternating automaton representing the assertions. The alternating automaton may be non-deterministic. The system translates the alternating automaton to a finite state machine (FSM) that may be represented using a representation such as a register transfer level (RTL) representation. The system models existential transitions in the state machine using variables. As a result, the system generates fewer states in the state machine, thereby requiring significantly less memory resources for processing the assertion. The system validates the circuit design using the state machine for further design and manufacture of the circuit.

公开(公告)号：US09626468B2

公开(公告)日：2017-04-18

申请号：US14192809

申请日：2014-02-27

Applicant: Synopsys, Inc.

Inventor： Eduard Cerny ,  Diganchal Chakraborty ,  Saptarshi Ghosh ,  Yogesh Pandey

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5045

Abstract: Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification.

公开(公告)号：US20190340327A1

公开(公告)日：2019-11-07

申请号：US16297324

申请日：2019-03-08

Applicant: Synopsys, Inc.

Inventor： Saptarshi Ghosh ,  Yogesh Pandey ,  Sivaprasad Acharya ,  Eduard Cerny

IPC: G06F17/50

Abstract: A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.

公开(公告)号：US20150242541A1

公开(公告)日：2015-08-27

申请号：US14192809

申请日：2014-02-27

Applicant: Synopsys, Inc.

Inventor： Eduard Cerny ,  Diganchal Chakraborty ,  Saptarshi Ghosh ,  Yogesh Pandey

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5045

Abstract: Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification.

Abstract translation: 识别电子设计中可以生成有趣的断言（例如断言，假设和覆盖属性）的信号组。 使用固定深度的滑动时间窗口来对由一个或多个模拟或仿真产生的信号组中的信号的唯一现有和过去值组合进行采样。 信号组中的信号值被组织成真值表。 使用类似于从痕迹合​​成部分有限存储器的技术，从真值表中提取最小的函数关系，并用于生成断言。 使用成本函数和针对性启发式过滤该断言，以及用于修剪无法访问的属性并生成可达覆盖属性的跟踪的形式验证工具。 语法正确的断言，假设和覆盖生成的属性的属性语句被实例化并打包成适合进一步仿真或仿真或正式验证的文件。

公开(公告)号：US11544435B1

公开(公告)日：2023-01-03

申请号：US17353208

申请日：2021-06-21

Applicant: Synopsys, Inc.

Inventor： Dmitry Korchemny ,  Ilya Kudryavtsev ,  Eduard Cerny ,  Dmitriy Mosheyev

IPC: G06F30/3308 ,  G06F30/38 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

公开(公告)号：US20180157776A1

公开(公告)日：2018-06-07

申请号：US15827202

申请日：2017-11-30

Applicant: Synopsys, Inc.

Inventor： Eduard Cerny ,  Gerald Taylor

IPC: G06F17/50

Abstract: A system receive as input a circuit design and a description of the behavior of the circuit design specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. The system generates an alternating automaton representing the assertions. The alternating automaton may be non-deterministic. The system translates the alternating automaton to a finite state machine (FSM) that may be represented using a representation such as a register transfer level (RTL) representation. The system models existential transitions in the state machine using variables. As a result, the system generates fewer states in the state machine, thereby requiring significantly less memory resources for processing the assertion. The system validates the circuit design using the state machine for further design and manufacture of the circuit.