公开(公告)号：US11797735B1

公开(公告)日：2023-10-24

申请号：US17194147

申请日：2021-03-05

Applicant: Synopsys, Inc.

Inventor： Boris Gommershtadt ,  Leonid Greenberg ,  Ilya Kudryavtsev ,  Yaron Shkedi

IPC: G06F30/327 ,  G06F30/3308 ,  G06F30/3323 ,  G06F30/398 ,  G06F30/367 ,  G06F17/18 ,  G06N7/00 ,  G06N7/01

CPC classification number: G06F30/327 ,  G06N7/01 ,  G06F17/18 ,  G06F30/3308 ,  G06F30/3323 ,  G06F30/367 ,  G06F30/398

Abstract: A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results, (ii) changes to the product since a previous estimation or regression test has been performed and (iii) information regarding a user. The method includes identifying a candidate test having a confidence score that is below a threshold, in response to the identification of the candidate test, performing the candidate test, and providing, to a user, results of the performing of the candidate test.

公开(公告)号：US11544435B1

公开(公告)日：2023-01-03

申请号：US17353208

申请日：2021-06-21

Applicant: Synopsys, Inc.

Inventor： Dmitry Korchemny ,  Ilya Kudryavtsev ,  Eduard Cerny ,  Dmitriy Mosheyev

IPC: G06F30/3308 ,  G06F30/38 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

公开(公告)号：US11501050B1

公开(公告)日：2022-11-15

申请号：US17176993

申请日：2021-02-16

Applicant: Synopsys, Inc.

Inventor： Dmitry Korchemny ,  Eduard R. Cerny ,  Ilya Kudryavtsev

IPC: G06F119/02 ,  G06F30/367 ,  G06F30/38

Abstract: A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

公开(公告)号：US20240273271A1

公开(公告)日：2024-08-15

申请号：US18167861

申请日：2023-02-12

Applicant: Synopsys, Inc.

Inventor： Dmitry Korchemny ,  Naphtali Yehoshua Sprei ,  Ilya Kudryavtsev

IPC: G06F30/33 ,  G06F30/327

CPC classification number: G06F30/33 ,  G06F30/327 ,  G06F2119/02

Abstract: An assertion for a sequential implication for a circuit design is received. The sequential implication defines a nonoverlapping transaction in which new transactions are not allowed while an existing transaction is still pending. The assertion is converted to a deterministic finite automaton on finite words in a machine-readable form, which is made available to verify the operation of the circuit design.

公开(公告)号：US11106663B1

公开(公告)日：2021-08-31

申请号：US16283639

申请日：2019-02-22

Applicant: Synopsys, Inc.

Inventor： Ilya Kudryavtsev ,  Daniel Geist ,  Boris Gommershtadt

IPC: G06F16/242 ,  G06F16/22

Abstract: A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.