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1.发明授权Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM 失效在DRAM，SRAM和ROM之间利用单个复用地址总线的方法
公开(公告)号：US5901298A
公开(公告)日：1999-05-04
申请号：US726700
申请日：1996-10-07
CPC分类号： G06F13/4243
摘要： A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.
摘要翻译： 用于在本地总线和存储器总线之间进行接口的存储器接口装置。 存储器总线耦合到静态存储器和动态存储器。 接口设备包括耦合到选择设备的第一和第二内部总线。 选择装置将第一和第二内部总线中的一个选择性地耦合到存储器总线。 存储器接口设备还包括接口控制单元，其具有耦合到本地总线的输入，用于接收地址和控制信号。 接口控制单元还具有耦合到第一内部总线的输出，用于响应于地址和控制信号而在脉冲串中产生门控每个数据传输。
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2.发明授权Method and apparatus for inserting an error signal onto a bidirectional signal line 有权将误差信号插入到双向信号线上的方法和装置
公开(公告)号：US6067647A
公开(公告)日：2000-05-23
申请号：US146455
申请日：1998-09-02
申请人： T. Scott Cummins
发明人： T. Scott Cummins
IPC分类号： G06F11/26 , G06F11/267 , G06F11/00
CPC分类号： G06F11/2215 , G06F11/261
摘要： One embodiment of the present invention includes an apparatus for inserting an error signal onto a bidirectional signal line. The apparatus includes a first switch for decoupling a first terminal of the bidirectional signal line from a second terminal of the bidirectional signal line, a second switch for coupling the error signal to the first terminal, and a third switch for coupling the error signal to the second terminal. The apparatus also includes a control unit for generating a switch enable signal. When the switch enable signal is deasserted, the first switch closes and the second and third switches open, such that the first terminal is coupled to the second terminal. When the switch enable signal is asserted, the first switch opens and the second and third switches close, such that the error signal is coupled to the first and second terminals.
摘要翻译： 本发明的一个实施例包括用于在双向信号线上插入误差信号的装置。 该装置包括用于将双向信号线的第一端与双向信号线的第二端分离的第一开关，用于将误差信号耦合到第一端的第二开关和用于将误差信号耦合到第二开关 第二个终端。 该装置还包括用于产生开关使能信号的控制单元。 当开关使能信号无效时，第一开关闭合，第二和第三开关断开，使得第一端子耦合到第二端子。 当开关使能信号被断言时，第一开关断开，第二和第三开关闭合，使得误差信号耦合到第一和第二端子。
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3.发明授权公开(公告)号：US06292910B1
公开(公告)日：2001-09-18
申请号：US09153095
申请日：1998-09-14
申请人： T. Scott Cummins
发明人： T. Scott Cummins
IPC分类号： G06F946
CPC分类号： G06F13/423
摘要： One embodiment of the present invention is an apparatus for detecting a bus deadlock in an electronic system. The apparatus includes a bus tracker circuit to monitor bus transactions to detect a condition that indicates the occurrence of a wait cycle or a retry cycle. The apparatus also includes a counter circuit to indicate that the bus tracker circuit has detected the condition a predetermined number of times.
摘要翻译： 本发明的一个实施例是一种用于检测电子系统中总线死锁的装置。 该装置包括总线跟踪器电路，用于监视总线事务以检测指示发生等待周期或重试周期的状况。 该装置还包括一个计数器电路，指示总线跟踪器电路已经检测到该条件预定次数。
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