公开(公告)号：US20180277199A1

公开(公告)日：2018-09-27

申请号：US15991739

申请日：2018-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

IPC: G11C11/419

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or the combination thereof, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.

公开(公告)号：US20170178719A1

公开(公告)日：2017-06-22

申请号：US15336633

申请日：2016-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.

公开(公告)号：US20170110461A1

公开(公告)日：2017-04-20

申请号：US15186446

申请日：2016-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/5283

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20200381043A1

公开(公告)日：2020-12-03

申请号：US16997857

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

IPC: G11C11/419

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

公开(公告)号：US20190393228A1

公开(公告)日：2019-12-26

申请号：US16562299

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768 ,  H01L21/321

Abstract: A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided.

公开(公告)号：US20230380129A1

公开(公告)日：2023-11-23

申请号：US18362786

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H10B10/00 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B10/12 ,  H01L27/0207 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/5283

Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

公开(公告)号：US20210265363A1

公开(公告)日：2021-08-26

申请号：US17320091

申请日：2021-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

公开(公告)号：US20180102907A1

公开(公告)日：2018-04-12

申请号：US15288382

申请日：2016-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen LIN ,  Shih-Lien Linus LU ,  Wei-Min CHAN

IPC: H04L9/32 ,  G06F21/44 ,  G06F21/73 ,  G06F12/14

CPC classification number: H04L9/3278 ,  G06F12/1408 ,  G06F21/44 ,  G06F21/73 ,  G06F2212/1052 ,  G06F2212/402

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.