公开(公告)号：US20220367456A1

公开(公告)日：2022-11-17

申请号：US17816044

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Shuo CHEN ,  Chia-Der CHANG ,  Yi-Jing LEE

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

公开(公告)号：US20180175031A1

公开(公告)日：2018-06-21

申请号：US15895987

申请日：2018-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Kun-Mu LI ,  Ming-Hua YU ,  Tsz-Mei KWOK

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/7848

Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.

公开(公告)号：US20240203987A1

公开(公告)日：2024-06-20

申请号：US18415143

申请日：2024-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Kun-Mu LI ,  Ming-Hua YU ,  Tsz-Mei KWOK

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/7848

Abstract: An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

公开(公告)号：US20170133386A1

公开(公告)日：2017-05-11

申请号：US14938311

申请日：2015-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Kun-Mu LI

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7853

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

公开(公告)号：US20230124966A1

公开(公告)日：2023-04-20

申请号：US18069765

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Kun-Mu LI

IPC: H10B10/00 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

公开(公告)号：US20190006491A1

公开(公告)日：2019-01-03

申请号：US15801097

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Ming-Hua YU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/04 ,  H01L29/78

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

公开(公告)号：US20210074710A1

公开(公告)日：2021-03-11

申请号：US17089580

申请日：2020-11-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Kun-Mu LI

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.

公开(公告)号：US20200176581A1

公开(公告)日：2020-06-04

申请号：US16693988

申请日：2019-11-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Chih-Shin KO ,  Clement Hsingjen WANN

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

公开(公告)号：US20180006039A1

公开(公告)日：2018-01-04

申请号：US15702569

申请日：2017-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Kun-Mu LI

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7853

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

公开(公告)号：US20240397692A1

公开(公告)日：2024-11-28

申请号：US18791000

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Kun-Mu LI

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

Abstract: A device includes a semiconductor channel region over a substrate, a shallow trench isolation (STI) region in the substrate, a gate structure over the semiconductor channel region. The semiconductor channel region has a channel top higher than a top surface of the STI region by a first height. The device further includes a first source/drain epitaxy structure and a second source/drain epitaxy structure respectively at opposite sides of the gate structure, and a first dielectric fin sidewall structure and a second dielectric fin sidewall structure on opposite sides of the first source/drain epitaxy structure, respectively. A top of the first dielectric fin sidewall structure is higher than the top surface of the STI region by a second height. The second height is at most half the first height.