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公开(公告)号：US12107581B2
公开(公告)日：2024-10-01
申请号：US18362916
申请日：2023-07-31
Inventor： Seid Hadi Rasouli , Jerry Chang Jui Kao , Xiangdong Chen , Tzu-Ying Lin , Yung-Chen Chien , Hui-Zhong Zhuang , Chi-Lin Liu
Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.
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公开(公告)号：US11870441B2
公开(公告)日：2024-01-09
申请号：US18065327
申请日：2022-12-13
Inventor： Seid Hadi Rasouli , Jerry Chang Jui Kao , Xiangdong Chen , Tzu-Ying Lin , Yung-Chen Chien , Hui-Zhong Zhuang , Chi-Lin Liu
Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.
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公开(公告)号：US11152923B2
公开(公告)日：2021-10-19
申请号：US16538221
申请日：2019-08-12
Inventor： Chi-Lin Liu , Shang-Chih Hsieh , Lee-Chung Lu , Chang-Yu Wu
IPC: H03K3/356 , G01R31/3185 , H03K3/037
Abstract: A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on at least a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have a first voltage swing or a second voltage swing based on the first output signal and the second output signal. The first voltage swing is different from the second voltage swing.
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公开(公告)号：US09356583B2
公开(公告)日：2016-05-31
申请号：US14472937
申请日：2014-08-29
Inventor： Chi-Lin Liu , Shang-Chih Hsieh , Lee-Chung Lu , Chang-Yu Wu
CPC classification number: H03K3/356104 , G01R31/318541 , H03K3/037 , H03K3/356121
Abstract: A flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first state of a clock signal, and provide a first output signal. The trigger stage receives the clock signal and the first output signal to provide a trigger signal. The trigger signal does not toggle as the clock signal transits. The second latch is configured to latch the trigger signal in response to a second state of the clock signal, and provide a second output signal. The first state and the second state of the clock signal are complementary to each other.
Abstract translation: 触发器电路包括第一锁存器，触发级和第二锁存器。 第一锁存器被配置为响应于时钟信号的第一状态来锁存所选择的信号，并且提供第一输出信号。 触发级接收时钟信号和第一输出信号以提供触发信号。 随着时钟信号的转换，触发信号不会切换。 第二锁存器被配置为响应于时钟信号的第二状态来锁存触发信号，并提供第二输出信号。 时钟信号的第一状态和第二状态彼此互补。
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公开(公告)号：US12301228B2
公开(公告)日：2025-05-13
申请号：US18644156
申请日：2024-04-24
Inventor： Greg Gruber , Chi-Lin Liu , Ming-Chang Kuo , Lee-Chung Lu , Shang-Chih Hsieh
IPC: H03K19/00 , G01R31/3185
Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
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Patent Agency Ranking
公开(公告)号：US12074603B1
公开(公告)日：2024-08-27
申请号：US18313384
申请日：2023-05-08
Inventor： Yu-Jheng Ou-Yang , Chi-Lin Liu , Shang-Chih Hsieh , Wei-Hsiang Ma , Kai-Chi Huang
IPC: H03K3/037 , H03K3/3562
CPC classification number: H03K3/0372 , H03K3/0375 , H03K3/35625
Abstract: The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.
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公开(公告)号：US20240056061A1
公开(公告)日：2024-02-15
申请号：US18448027
申请日：2023-08-10
Inventor： Chi-Lin Liu , Shang-Chih Hsieh , Wei-Hsiang Ma
Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.
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公开(公告)号：US11757435B2
公开(公告)日：2023-09-12
申请号：US17815679
申请日：2022-07-28
Inventor： Kai-Chi Huang , Yung-Chen Chien , Chi-Lin Liu , Wei-Hsiang Ma , Jerry Chang Jui Kao , Shang-Chih Hsieh , Lee-Chung Lu
IPC: H03K3/037 , G06F1/3237 , H03K3/356 , H03K19/00
CPC classification number: H03K3/0375 , G06F1/3237 , H03K3/0372 , H03K3/356086 , H03K19/0016
Abstract: A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.
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公开(公告)号：US11694012B2
公开(公告)日：2023-07-04
申请号：US17853095
申请日：2022-06-29
Inventor： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC: G06F30/30 , H01L27/02 , G06F30/392 , G06F30/347 , G06F30/39
CPC classification number: G06F30/392 , G06F30/347 , G06F30/39 , H01L27/0207
Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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公开(公告)号：US20220327275A1
公开(公告)日：2022-10-13
申请号：US17853095
申请日：2022-06-29
Inventor： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC: G06F30/392 , G06F30/39 , H01L27/02
Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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