公开(公告)号：US10970450B2

公开(公告)日：2021-04-06

申请号：US15782232

申请日：2017-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Ho Che Yu ,  Lee-Chung Lu ,  Ni-Wan Fan ,  Po-Hsiang Huang ,  Chi-Yu Lu ,  Jeo-Yen Lee

IPC: G06F30/392 ,  H01L27/118 ,  G06F30/398 ,  G06F30/39 ,  H01L23/538 ,  H01L27/02

Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.

公开(公告)号：US11281836B2

公开(公告)日：2022-03-22

申请号：US17222021

申请日：2021-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Ho Che Yu ,  Lee-Chung Lu ,  Ni-Wan Fan ,  Po-Hsiang Huang ,  Chi-Yu Lu ,  Jeo-Yen Lee

IPC: G06F30/392 ,  H01L27/118 ,  G06F30/398 ,  G06F30/39 ,  H01L23/538 ,  H01L27/02

Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.

公开(公告)号：US10396063B2

公开(公告)日：2019-08-27

申请号：US15264168

申请日：2016-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Fong-Yuan Chang ,  Lee-Chung Lu ,  Yi-Kan Cheng ,  Sheng-Hsiung Chen ,  Po-Hsiang Huang ,  Shun Li Chen ,  Jeo-Yen Lee ,  Jyun-Hao Chang ,  Shao-Huan Wang ,  Chien-Ying Chen

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118

Abstract: In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.