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公开(公告)号：US11275886B2
公开(公告)日：2022-03-15
申请号：US17235262
申请日：2021-04-20
发明人： Sheng-Hsiung Chen , Wen-Hao Chen , Chun-Yao Ku , Shao-Huan Wang , Hung-Chih Ou
IPC分类号： G06F30/30 , G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F115/06 , G06F119/06 , G06F119/12 , G06F30/392
摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
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公开(公告)号：US10396063B2
公开(公告)日：2019-08-27
申请号：US15264168
申请日：2016-09-13
发明人： Fong-Yuan Chang , Lee-Chung Lu , Yi-Kan Cheng , Sheng-Hsiung Chen , Po-Hsiang Huang , Shun Li Chen , Jeo-Yen Lee , Jyun-Hao Chang , Shao-Huan Wang , Chien-Ying Chen
IPC分类号： H01L27/02 , G06F17/50 , H01L27/118
摘要： In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
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公开(公告)号：US11669669B2
公开(公告)日：2023-06-06
申请号：US16943827
申请日：2020-07-30
发明人： Chin-Shen Lin , Wan-Yu Lo , Shao-Huan Wang , Kuo-Nan Yang , Chung-Hsing Wang , Sheng-Hsiung Chen , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/392 , G06F30/347 , H01L21/78
CPC分类号： G06F30/392 , G06F30/347 , H01L21/78
摘要： A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.
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公开(公告)号：US11727185B2
公开(公告)日：2023-08-15
申请号：US17815013
申请日：2022-07-26
IPC分类号： G06F30/394 , G06F30/20 , G06F30/327 , G06F30/392 , G06F30/3312 , G06F30/373 , G06F30/33 , G06F30/337 , G06F30/398 , H01L23/52 , H01L23/522 , G06F111/04 , G06F119/12
CPC分类号： G06F30/394 , G06F30/20 , G06F30/327 , G06F30/3312 , G06F30/392 , G06F30/33 , G06F30/337 , G06F30/373 , G06F30/398 , G06F2111/04 , G06F2119/12 , H01L23/5226
摘要： A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.
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公开(公告)号：US10678991B2
公开(公告)日：2020-06-09
申请号：US16020132
申请日：2018-06-27
发明人： Chun-Yao Ku , Wen-Hao Chen , Ming-Tao Yu , Shao-Huan Wang , Jyun-Hao Chang
IPC分类号： G06F17/50 , G06F30/398 , G06F30/394 , G06F119/10
摘要： A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.
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公开(公告)号：US09977857B1
公开(公告)日：2018-05-22
申请号：US15600410
申请日：2017-05-19
发明人： Chun-Yao Ku , Hung-Chih Ou , Shao-Huan Wang , Wen-Hao Chen , Ming-Tao Yu
IPC分类号： H01L21/82 , G06F17/50 , H01L23/522
CPC分类号： G06F17/5081 , G06F17/5077 , H01L23/5226
摘要： In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.
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公开(公告)号：US12014131B2
公开(公告)日：2024-06-18
申请号：US18337245
申请日：2023-06-19
发明人： Sheng-Hsiung Chen , Wen-Hao Chen , Hung-Chih Ou , Chun-Yao Ku , Shao-Huan Wang
IPC分类号： G06F30/30 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F30/398 , G06F30/392 , G06F115/06 , G06F119/06 , G06F119/12
CPC分类号： G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F30/392 , G06F2115/06 , G06F2119/06 , G06F2119/12
摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
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公开(公告)号：US11855632B2
公开(公告)日：2023-12-26
申请号：US17115571
申请日：2020-12-08
IPC分类号： H03K19/17704 , H01L23/528 , H03K19/17736 , H01L27/02 , G06F30/392
CPC分类号： H03K19/17704 , G06F30/392 , H01L23/528 , H01L27/0207 , H03K19/17736
摘要： A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.
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公开(公告)号：US10990745B2
公开(公告)日：2021-04-27
申请号：US16559534
申请日：2019-09-03
发明人： Sheng-Hsiung Chen , Shao-Huan Wang , Wen-Hao Chen , Chun-Yao Ku , Hung-Chih Ou
IPC分类号： G06F17/50 , G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G03F1/70 , G03F1/36 , G06F30/394 , G06F115/06 , G06F119/06 , G06F119/12 , G06F30/392
摘要： An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.
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公开(公告)号：US11681853B2
公开(公告)日：2023-06-20
申请号：US17692767
申请日：2022-03-11
发明人： Sheng-Hsiung Chen , Wen-Hao Chen , Hung-Chih Ou , Chun-Yao Ku , Shao-Huan Wang
IPC分类号： G06F30/30 , G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F115/06 , G06F119/06 , G06F119/12 , G06F30/392
CPC分类号： G06F30/398 , G06F30/337 , G06F30/3315 , G06F30/396 , G06F30/392 , G06F2115/06 , G06F2119/06 , G06F2119/12
摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
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