-
公开(公告)号：US20240387507A1
公开(公告)日：2024-11-21
申请号：US18789539
申请日：2024-07-30
Inventor： Li-Wei CHU , Wun-Jie LIN , Yu-Ti SU , Ming-Fu TSAI , Jam-Wem LEE
Abstract: A method of making a semiconductor device includes manufacturing lines extending in a first direction over doped zones in a substrate, wherein each of the lines has a line width measured along a first direction. The method further includes trimming the lines into line segments having ends over an isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the first direction, and the line width is substantially similar to the gate electrode width.
-
Patent Agency Ranking
公开(公告)号：US20220344929A1
公开(公告)日：2022-10-27
申请号：US17452281
申请日：2021-10-26
Inventor： Chia-Lin HSU , Ming-Fu TSAI , Yu-Ti SU , Kuo-Ji CHEN
Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.
-
公开(公告)号：US20240120735A1
公开(公告)日：2024-04-11
申请号：US18545851
申请日：2023-12-19
Inventor： Chia-Lin HSU , Ming-Fu TSAI , Yu-Ti SU , Kuo-Ji CHEN
CPC classification number: H02H9/046 , H01L27/0255 , H01L27/0259 , H01L27/0266 , H02H1/0007 , H01L27/0288
Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.
-
公开(公告)号：US20230068649A1
公开(公告)日：2023-03-02
申请号：US17459878
申请日：2021-08-27
Inventor： Li-Wei CHU , Wun-Jie LIN , Yu-Ti SU , Ming-Fu TSAI , Jam-Wem LEE
Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.
-
公开(公告)号：US20240047453A1
公开(公告)日：2024-02-08
申请号：US18489652
申请日：2023-10-18
Inventor： Li-Wei CHU , Wun-Jie LIN , Yu-Ti SU , Ming-Fu TSAI , Jam-Wem LEE
CPC classification number: H01L27/0248 , H01L29/0649
Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
-
公开(公告)号：US20170346479A1
公开(公告)日：2017-11-30
申请号：US15450330
申请日：2017-03-06
Inventor： Ming-Fu TSAI , Jen-Chou TSENG , Kuo-Ji CHEN , Tzu-Heng CHANG
IPC: H03K17/0814 , H03K5/08
CPC classification number: H03K17/08142 , H03K5/08 , H03K19/00315
Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.
-
-
-
-
-
Search Results
6
records
(took 0.02 seconds)
