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    ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND METHOD OF OPERATING THE SAME
    2.
    发明公开
    ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230238793A1

    公开(公告)日：2023-07-27

    申请号：US18128693

    申请日：2023-03-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yu-Hung YEH ,  Wun-Jie LIN ,  Jam-Wem LEE

    IPC: H02H3/08 ,  H02H1/00

    CPC classification number: H02H3/08 ,  H02H1/0007

    Abstract: An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

    CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS
    4.
    发明申请
    CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS 有权
    具有层间VIAS和内层耦合晶体管的电路

    公开(公告)号：US20150187747A1

    公开(公告)日：2015-07-02

    申请号：US14658613

    申请日：2015-03-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Jam-Wem LEE

    IPC: H01L27/02 ,  H01L27/088 ,  H01L27/092

    CPC classification number: H01L27/0207 ,  H01L25/11 ,  H01L25/50 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line coupling a drain of the first transistor with a gate of the second transistor. The circuit also comprises a second layer comprising a second voltage line, a third transistor coupled with the second voltage line, a fourth transistor coupled with the second voltage line, and a second line coupling a drain of the third transistor with a gate of the fourth transistor. The circuit further comprises an inter-layer interconnect structure coupling the first transistor with the third transistor, and the second transistor with the fourth transistor.

    Abstract translation: 电路包括第一层，第一层包括第一电压线，与第一电压线耦合的第一晶体管，与第一电压线耦合的第二晶体管，以及将第一晶体管的漏极与第二晶体管的栅极耦合的第一线 。 该电路还包括第二层，其包括第二电压线，与第二电压线耦合的第三晶体管，与第二电压线耦合的第四晶体管，以及将第三晶体管的漏极与第四电压线的第四 晶体管。 电路还包括将第一晶体管与第三晶体管耦合的层间互连结构，以及具有第四晶体管的第二晶体管。

    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME
    6.
    发明申请
    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME 有权

    公开(公告)号：US20240387515A1

    公开(公告)日：2024-11-21

    申请号：US18788783

    申请日：2024-07-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chia-Wei HSU ,  Bo-Ting CHEN ,  Jam-Wem LEE

    IPC: H01L27/02

    Abstract: An integrated circuit (IC) device includes a substrate having a front side, a back side below the front side, and first functional circuitry and a first electrostatic discharge (ESD) clamp circuit on the front side of the substrate. The IC device further includes a first connection tower that extends below the back side of the substrate and is connected to an input/output pad below the back side of the substrate, and one or more first front side conductors and one or more first front side vias which connect the first buried connection tower to the first functional circuitry and to the first ESD clamp circuit.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    9.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权

    公开(公告)号：US20220285336A1

    公开(公告)日：2022-09-08

    申请号：US17354870

    申请日：2021-06-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tzu-Hao CHIANG ,  Wun-Jie LIN ,  Jam-Wem LEE

    IPC: H01L27/02 ,  H01L29/06

    Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

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