公开(公告)号：US11798836B2

公开(公告)日：2023-10-24

申请号：US17350930

申请日：2021-06-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Yu Yang ,  Po-Wei Liu ,  Yun-Chi Wu ,  Yu-Wen Tseng ,  Chia-Ta Hsieh ,  Ping-Cheng Li ,  Tsung-Hua Yang ,  Yu-Chun Chang

IPC分类号： H01L21/762 ,  H01L21/74 ,  H01L23/535

CPC分类号： H01L21/76283 ,  H01L21/743 ,  H01L23/535

摘要： A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

公开(公告)号：US11574918B2

公开(公告)日：2023-02-07

申请号：US17340704

申请日：2021-06-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yun-Chi Wu ,  Yu-Wen Tseng

IPC分类号： H01L27/1157 ,  H01L29/423 ,  H01L27/12 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/792 ,  H01L29/775 ,  H01L27/11568

摘要： A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

公开(公告)号：US11670689B2

公开(公告)日：2023-06-06

申请号：US17471722

申请日：2021-09-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Wen Tseng ,  Po-Wei Liu ,  Hung-Ling Shih ,  Tsung-Yu Yang ,  Tsung-Hua Yang ,  Yu-Chun Chang

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/401 ,  H01L29/0653 ,  H01L29/423 ,  H01L29/7823

摘要： A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.