公开(公告)号：US11493563B2

公开(公告)日：2022-11-08

申请号：US16668986

申请日：2019-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsieh-Hung Hsieh ,  Wu-Chen Lin ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/40 ,  H03F3/21

Abstract: A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

公开(公告)号：US11906598B2

公开(公告)日：2024-02-20

申请号：US17818141

申请日：2022-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsieh-Hung Hsieh ,  Wu-Chen Lin ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/40 ,  H03F3/21 ,  G01R29/08 ,  H03F3/24

CPC classification number: G01R31/40 ,  G01R29/0871 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/267 ,  H03F2200/451

Abstract: A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.