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    Test circuit and method
    3.
    发明授权
    Test circuit and method 有权

    公开(公告)号：US11768235B2

    公开(公告)日：2023-09-26

    申请号：US18151959

    申请日：2023-01-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

    IPC: G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2853 ,  G01R31/2879

    Abstract: An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.

    Test circuit and method
    4.
    发明授权
    Test circuit and method 有权

    公开(公告)号：US11555848B2

    公开(公告)日：2023-01-17

    申请号：US17376338

    申请日：2021-07-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

    IPC: G01R31/28

    Abstract: A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

    Phase frequency detector circuit
    5.
    发明授权
    Phase frequency detector circuit 有权
    相位检波电路

    公开(公告)号：US09374038B2

    公开(公告)日：2016-06-21

    申请号：US14133982

    申请日：2013-12-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yen-Jen Chen ,  I-Ting Lee ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC: H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    CPC classification number: H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    Abstract translation: 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

    Circuit and operating method of PLL
    6.
    发明授权
    Circuit and operating method of PLL 有权
    PLL的电路和操作方法

    公开(公告)号：US09432030B2

    公开(公告)日：2016-08-30

    申请号：US14097504

    申请日：2013-12-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yen-Jen Chen ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC: H03L7/06 ,  H03L7/087

    CPC classification number: H03L7/087 ,  H03L7/0898

    Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.

    Abstract translation: 锁相环（PLL）包括压控振荡器（VCO），环路滤波器和反馈控制单元。 VCO被配置为根据VCO控制信号产生第一振荡信号和第二振荡信号。 环路滤波器被配置为通过对环路滤波器的输入节点处的信号进行低通滤波来输出VCO控制信号。 所述反馈控制单元具有耦合到所述环路滤波器的输入节点的输出节点，所述反馈控制单元被配置为在可变周期期间沿着第一电流方向将第一预定量的电流施加到所述第一反馈控制输出节点 的时间 并且在预定时间段期间沿着与第一电流方向相反的第二电流方向将K个第二预定量的电流中的一个施加到第一反馈控制输出节点。

    Phase-locked loops that share a loop filter and frequency divider
    7.
    发明授权
    Phase-locked loops that share a loop filter and frequency divider 有权
    共振环路滤波器和分频器的锁相环路

    公开(公告)号：US08963595B2

    公开(公告)日：2015-02-24

    申请号：US14444385

    申请日：2014-07-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Feng Wei Kuo ,  Shyh-An Chi ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    IPC: H03L7/06 ,  H03L7/07 ,  H03L7/093 ,  H03L7/099

    CPC classification number: H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    Abstract: A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.

    Abstract translation: 共享环路滤波器包括被配置为选择性地接收来自第一电荷泵的第一输入的输入端口。 第一电荷泵连接到第一芯片中的第一锁相环（PLL）。 所述输入端口还被配置为选择性地从第二电荷泵接收第二输入，所述第二电荷泵连接到与所述第一裸片分开的第二模具中的第二PLL。 共享环路滤波器还包括被配置为选择性地向第一压控振荡器（VCO）提供输出的输出端口。 第一个VCO连接到第一个PLL。 输出端口还被配置为选择性地将第二输出输出到第二VCO。 第二个VCO连接到第二个PLL。

    Phase-locked loops that share a loop filter
    10.
    发明授权
    Phase-locked loops that share a loop filter 有权
    共享环路滤波器的锁相环路

    公开(公告)号：US08816731B2

    公开(公告)日：2014-08-26

    申请号：US14025125

    申请日：2013-09-12

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Feng Wei Kuo ,  Shyh-An Chi ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    IPC: H03L7/06

    CPC classification number: H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.

    Abstract translation: 集成电路包括第一管芯和第二管芯。 第一管芯包括第一锁相环（PLL），第二管芯包括第二PLL。 集成电路包括共享环路滤波器，其中第一管芯中的第一PLL与共享环路滤波器组合以形成第一PLL反馈环路，第二管芯中的第二PLL与共享环路滤波器组合以形成第二PLL PLL反馈环路和共享环路滤波器被配置为向第一PLL反馈环路和第二PLL反馈环路中的每一个提供可配置带宽。

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