公开(公告)号：US20240161677A1

公开(公告)日：2024-05-16

申请号：US17780981

申请日：2022-05-25

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD.

Inventor： Donghun LIM ,  Hui YANG

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0267 ,  G09G2310/08

Abstract: The present application provides a GOA circuit and a display panel. The GOA circuit includes a plurality of cascaded GOA units, and an nth stage GOA unit only includes a pull-up control module, a pull-up output module, a pull-down module, and a pull-down maintenance module. Moreover, the pull-down maintenance module receives a clock signal and can pull down a potential of a pull-up node under a control of the clock signal, so as to reduce a working time of the pull-down maintenance module and prolong a working life of the pull-down maintenance module, thereby improving working stability of the GOA circuit.

公开(公告)号：US20220076605A1

公开(公告)日：2022-03-10

申请号：US15734884

申请日：2020-10-19

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Hui YANG ,  Xiang GAO

IPC: G09G3/20 ,  G09G3/36

Abstract: The present application provides a display panel adjustment method and an adjustment method for a display panel. A fan-out mura region of the display panel is divided into multiple first sub-regions along a first direction; according to an initial grayscale value of a first bonding point in the first sub-region, the fan-out mura degree and a first correction value of the corresponding first sub-region are obtained; and then grayscale compensation is performed on the corresponding first sub-region. The present application improves the mura effects in the fan-out region and improves the display quality of a product.

公开(公告)号：US20240178241A1

公开(公告)日：2024-05-30

申请号：US18191701

申请日：2023-03-28

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Hui YANG ,  Fan YANG

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362

CPC classification number: H01L27/1255 ,  G02F1/134309 ,  G02F1/13606 ,  G02F1/136213 ,  G02F1/136286 ,  H01L27/124 ,  G02F2201/40

Abstract: The present application provides an array substrate, the array substrate includes a gate electrode, a compensation electrode, an array substrate side common electrode, and a source electrode. Disposing a source electrode portion and a compensation portion of the source electrode on two opposite sides of a storage capacitor portion and connecting the source electrode portion and the compensation portion to the storage capacitor portion can reduce an occupying area of the source electrode to improve an aperture rate of the array substrate.

公开(公告)号：US20240006537A1

公开(公告)日：2024-01-04

申请号：US17870541

申请日：2022-07-21

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Hui YANG ,  Yani CHEN

IPC: H01L29/786 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L29/401 ,  H01L29/66765

Abstract: The present application provides an array substrate including at least a gate layer, a gate insulation layer, an active layer, and a light blocking layer, wherein the gate insulation layer and the active layer are disposed sequentially on the gate layer, the gate insulation layer has a central region overlapped with the active layer and a peripheral region surrounding the central region, the active layer has a first surface away from the gate insulation layer, and the gate insulation layer has a third surface located in the central region and in contact with the active layer, and the light blocking layer is disposed in the peripheral region and having a second surface away from the gate insulation layer, wherein a height of the second surface relative to the third surface is greater than a height of the first surface relative to the third surface.