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公开(公告)号：US20250118717A1
公开(公告)日：2025-04-10
申请号：US18523947
申请日：2023-11-30
Inventor： Zhichao ZHOU , Zhiwei TAN
Abstract: An array substrate and a manufacturing method therefor, and a display panel. The array substrate includes a substrate, a first transistor and a photosensitive element; the first transistor and the photosensitive element are disposed on the substrate; the first transistor and the photosensitive element are electrically connected; the first transistor includes a first gate, a first active layer, a second gate stacked, and a source and a drain; the source and the drain are electrically connected to the first active layer respectively; the photosensitive element includes a first electrode, a photosensitive layer, and a second electrode stacked; the first electrode is disposed in the same layer as the second gate, and are electrically connected to the source or drain.
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公开(公告)号：US20240047599A1
公开(公告)日：2024-02-08
申请号：US17594046
申请日：2021-06-15
Inventor： Zhiwei TAN
IPC: H01L31/113 , H01L31/0392 , H01L31/0224
CPC classification number: H01L31/1136 , H01L31/03921 , H01L31/022408 , H01L31/022475 , H01L31/202
Abstract: A semiconductor device and a photosensitive device are provided. The semiconductor device includes a substrate and a photosensitive thin film transistor. The photosensitive thin film transistor includes a first metal layer, an insulating layer, a photosensitive semiconductor layer, a photosensitive ohmic contact layer, and a second metal layer. At least one side of the photosensitive ohmic contact layer protrudes from the second metal layer arranged on it, which increases an irradiated area of the photosensitive ohmic contact layer, thereby improving a photo-responsiveness of the photosensitive thin film transistor.
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公开(公告)号：US20230161209A1
公开(公告)日：2023-05-25
申请号：US17051457
申请日：2020-05-20
Inventor： Zhixiong JIANG , Sheng SUN , Yoonsung UM , Woosung SON , Meng CHEN , Wuguang LIU , Jubin LI , Zhiwei TAN , Haiyan QUAN , Kaili QU , Chuwei LIANG , Ziqi LIU , Lintao LIU , Ting LI , Sikun HAO
IPC: G02F1/1368 , G02F1/1343 , G02F1/1362 , G02F1/1335 , H01L27/12
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/136286 , G02F1/133514 , H01L27/1222
Abstract: The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.
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公开(公告)号：US20230122931A1
公开(公告)日：2023-04-20
申请号：US17045186
申请日：2020-06-05
Inventor： Zhiwei TAN
IPC: H01L27/12 , H01L29/786 , H01L21/306 , H01L21/308 , H01L21/3213
Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.
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