CHARGE DEMULTIPLEXING HIGH-SPEED CMOS TIME DELAY AND INTEGRATION IMAGING

    公开(公告)号:US20230353908A1

    公开(公告)日:2023-11-02

    申请号:US18025748

    申请日:2020-10-30

    CPC classification number: H04N25/78 H04N25/768

    Abstract: Provided are apparatus, methods and techniques to perform a readout of a plurality (N) of Time Delay and Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes (SNs). The readout uses a plurality (N) of charge steering (CST) gates to steer and demultiplex respective charges from respective pixel registers to corresponding SNs. Output is provided from the SNs for producing respective digital values (e.g. through parallel conversion using ADCs). In an embodiment, charges are transferred vertically to the CSTs for demultiplexing horizontally to the SNs. The CSTs may be configured in a multi-stage configuration to assist with good charge transfer. The CSTs may be associated with a barrier implant to assist with proper charge steering.

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