公开(公告)号：US20230195658A1

公开(公告)日：2023-06-22

申请号：US17558278

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad WU ,  Abhishek SHANKAR ,  Mihir Narendra MODY ,  Gregory Raymond SHURTZ ,  Jason A. T. JONES ,  Hemant Vijay Kumar HARIYANI

IPC: G06F13/16

CPC classification number: G06F13/1647

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

公开(公告)号：US20240211414A1

公开(公告)日：2024-06-27

申请号：US18599649

申请日：2024-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad WU ,  Abhishek SHANKAR ,  Mihir Narendra MODY ,  Gregory Raymond SHURTZ ,  Jason A.T. JONES ,  Hemant Vijay Kumar HARIYANI

IPC: G06F13/16

CPC classification number: G06F13/1647

Abstract: Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.