公开(公告)号：US20200210351A1

公开(公告)日：2020-07-02

申请号：US16234508

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06F13/28 ,  H04N5/765 ,  G06T1/20

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20200242048A1

公开(公告)日：2020-07-30

申请号：US16256821

申请日：2019-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20200210205A1

公开(公告)日：2020-07-02

申请号：US16700254

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Denis Roland BEAUDOIN ,  Gregory Raymond SHURTZ ,  Santhanakrishnan Badri NARAYANAN ,  Mark Adrian BRYANS ,  Mihir Narendra MODY ,  Jason A.T. JONES ,  Jayant THAKUR

IPC: G06F9/4401 ,  H04L12/721 ,  H04L12/741 ,  H04L12/931 ,  H04L12/823 ,  G06F13/28

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20240211414A1

公开(公告)日：2024-06-27

申请号：US18599649

申请日：2024-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad WU ,  Abhishek SHANKAR ,  Mihir Narendra MODY ,  Gregory Raymond SHURTZ ,  Jason A.T. JONES ,  Hemant Vijay Kumar HARIYANI

IPC: G06F13/16

CPC classification number: G06F13/1647

Abstract: Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.

公开(公告)号：US20220114120A1

公开(公告)日：2022-04-14

申请号：US17558252

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20210209036A1

公开(公告)日：2021-07-08

申请号：US17073925

申请日：2020-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY ,  Jason A.T. JONES

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/42

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

公开(公告)号：US20230350811A1

公开(公告)日：2023-11-02

申请号：US18346309

申请日：2023-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20230326002A1

公开(公告)日：2023-10-12

申请号：US18333151

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Veeramanikandan RAJU ,  Niraj NANDAN ,  Samuel Paul VISALLI ,  Jason A.T. JONES ,  Kedar Satish CHITNIS ,  Gregory Raymond SHURTZ ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN

IPC: G06T7/00 ,  G06T1/20 ,  G06T3/40 ,  G05B23/02

CPC classification number: G06T7/0002 ,  G06T1/20 ,  G06T3/40 ,  H04N17/00 ,  G06T7/97 ,  G06T2207/10016 ,  G05B23/0259

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.

公开(公告)号：US20220012312A1

公开(公告)日：2022-01-13

申请号：US17487517

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deepak Kumar PODDAR ,  Mihir MODY ,  Veeramanikandan RAJU ,  Jason A.T. JONES

IPC: G06F21/16 ,  G06N3/04 ,  G06N20/00 ,  G06F21/12

Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

公开(公告)号：US20190205508A1

公开(公告)日：2019-07-04

申请号：US16188560

申请日：2018-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deepak Kumar PODDAR ,  Mihir MODY ,  Veeramanikandan RAJU ,  Jason A.T. JONES

IPC: G06F21/16 ,  G06F15/18 ,  G06N3/04

CPC classification number: G06F21/16 ,  G06N3/0472 ,  G06N20/00

Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.