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公开(公告)号：US20240211414A1
公开(公告)日：2024-06-27
申请号：US18599649
申请日：2024-03-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Daniel Brad WU , Abhishek SHANKAR , Mihir Narendra MODY , Gregory Raymond SHURTZ , Jason A.T. JONES , Hemant Vijay Kumar HARIYANI
IPC: G06F13/16
CPC classification number: G06F13/1647
Abstract: Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.
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公开(公告)号：US20200210256A1
公开(公告)日：2020-07-02
申请号：US16377404
申请日：2019-04-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kedar Satish CHITNIS , Charles Lance FUOCO , Sriramakrishnan GOVINDARAJAN , Mihir Narendra MODY , William A. MILLS , Gregory Raymond SHURTZ , Amritpal Singh MUNDRA
Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.
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公开(公告)号：US20240296220A1
公开(公告)日：2024-09-05
申请号：US18662227
申请日：2024-05-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kedar Satish CHITNIS , Mihir Narendra MODY , Amritpal Singh MUNDRA , Yashwant DUTT , Gregory Raymond SHURTZ , Robert John TIVY
CPC classification number: G06F21/54 , G06F9/485 , G06F21/554 , G06F21/79
Abstract: Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.
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公开(公告)号：US20230195658A1
公开(公告)日：2023-06-22
申请号：US17558278
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Daniel Brad WU , Abhishek SHANKAR , Mihir Narendra MODY , Gregory Raymond SHURTZ , Jason A. T. JONES , Hemant Vijay Kumar HARIYANI
IPC: G06F13/16
CPC classification number: G06F13/1647
Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.
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公开(公告)号：US20230185904A1
公开(公告)日：2023-06-15
申请号：US17550948
申请日：2021-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kedar Satish CHITNIS , Mihir Narendra MODY , Amritpal Singh MUNDRA , Yashwant DUTT , Gregory Raymond SHURTZ , Robert John TIVY
CPC classification number: G06F21/54 , G06F9/485 , G06F21/79 , G06F21/554
Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.
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Patent Agency Ranking
公开(公告)号：US20230350811A1
公开(公告)日：2023-11-02
申请号：US18346309
申请日：2023-07-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan GOVINDARAJAN , Gregory Raymond SHURTZ , Mihir Narendra MODY , Charles Lance FUOCO , Donald E. STEISS , Jonathan Elliot BERGSAGEL , Jason A.T. JONES
IPC: G06F12/1027 , G06F9/455
CPC classification number: G06F12/1027 , G06F9/45558 , G06F2009/45583 , G06F2212/657
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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公开(公告)号：US20230326002A1
公开(公告)日：2023-10-12
申请号：US18333151
申请日：2023-06-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY, JR. , Veeramanikandan RAJU , Niraj NANDAN , Samuel Paul VISALLI , Jason A.T. JONES , Kedar Satish CHITNIS , Gregory Raymond SHURTZ , Prithvi Shankar YEYYADI ANANTHA , Sriramakrishnan GOVINDARAJAN
CPC classification number: G06T7/0002 , G06T1/20 , G06T3/40 , H04N17/00 , G06T7/97 , G06T2207/10016 , G05B23/0259
Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.
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公开(公告)号：US20230016766A1
公开(公告)日：2023-01-19
申请号：US17945225
申请日：2022-09-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat SAGAR , Mihir Narendra MODY , Anthony Joseph LELL , Gregory Raymond SHURTZ
Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.
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公开(公告)号：US20210291735A1
公开(公告)日：2021-09-23
申请号：US17340207
申请日：2021-06-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat SAGAR , Mihir Narendra MODY , Anthony Joseph LELL , Gregory Raymond SHURTZ
Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.
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公开(公告)号：US20200242048A1
公开(公告)日：2020-07-30
申请号：US16256821
申请日：2019-01-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan GOVINDARAJAN , Gregory Raymond SHURTZ , Mihir Narendra MODY , Charles Lance FUOCO , Donald E. STEISS , Jonathan Elliot BERGSAGEL , Jason A.T. JONES
IPC: G06F12/1027 , G06F9/455
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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