LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES
    1.
    发明申请
    LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES 有权
    低成本和时序改进的架构,用于执行错误检查和校正系统中的记忆和业务,以及其他电路,系统和过程

    公开(公告)号:US20130246889A1

    公开(公告)日:2013-09-19

    申请号:US13860773

    申请日:2013-04-11

    Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

    Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路(110)一起使用的电子电路(200)。 电子电路(200)包括可在地址处访问的存储器电路(230),地址缓冲器(410),耦合到存储器电路(230)的数据缓冲器(440)和可在虚拟器件中操作的控制电路 循环,从存储器电路(230)中的下一个地址位置将数据从存储器电路(230)读取到数据缓冲器(440),并将该下一个地址存储在地址缓冲器(410)中。 电子电路还包括多路复用器(430),响应给定地址的比较电路(420)和地址缓冲器(410)中存储的地址,以操作多路复用器(430)以从数据缓冲器(440)传送数据 )或者从存储器电路(230)传递数据; 以及混合器电路(450),其可操作以将所述部分写入数据部分放入从所述数据缓冲器(440)或存储器电路(230)中选择的数据采集的数据中。 还公开了其它电路,设备,系统,操作过程和制造过程。

    Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
    2.
    发明授权
    Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes 有权
    低开销和时序改进的架构,用于对片上系统以及其他电路,系统和过程中的存储器和总线执行错误检查和校正

    公开(公告)号:US08671329B2

    公开(公告)日:2014-03-11

    申请号:US13860773

    申请日:2013-04-11

    Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

    Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路(110)一起使用的电子电路(200)。 电子电路(200)包括可在地址处访问的存储器电路(230),地址缓冲器(410),耦合到存储器电路(230)的数据缓冲器(440)和可在虚拟器件中操作的控制电路 循环,从存储器电路(230)中的下一个地址位置将数据从存储器电路(230)读取到数据缓冲器(440),并将该下一个地址存储在地址缓冲器(410)中。 电子电路还包括多路复用器(430),响应给定地址的比较电路(420)和地址缓冲器(410)中存储的地址,以操作多路复用器(430)以从数据缓冲器(440)传送数据 )或者从存储器电路(230)传递数据; 以及混合器电路(450),其可操作以将所述部分写入数据部分放入从所述数据缓冲器(440)或存储器电路(230)中选择的数据采集的数据中。 还公开了其它电路,设备,系统,操作过程和制造过程。

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