公开(公告)号：US20130246889A1

公开(公告)日：2013-09-19

申请号：US13860773

申请日：2013-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Kumar ,  Amit Kumar Dutta ,  Rubin A. Parekhji ,  Srivaths Ravi

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1052 ,  G11C8/06 ,  G11C8/16 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/19

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路（110）一起使用的电子电路（200）。 电子电路（200）包括可在地址处访问的存储器电路（230），地址缓冲器（410），耦合到存储器电路（230）的数据缓冲器（440）和可在虚拟器件中操作的控制电路 循环，从存储器电路（230）中的下一个地址位置将数据从存储器电路（230）读取到数据缓冲器（440），并将该下一个地址存储在地址缓冲器（410）中。 电子电路还包括多路复用器（430），响应给定地址的比较电路（420）和地址缓冲器（410）中存储的地址，以操作多路复用器（430）以从数据缓冲器（440）传送数据 ）或者从存储器电路（230）传递数据; 以及混合器电路（450），其可操作以将所述部分写入数据部分放入从所述数据缓冲器（440）或存储器电路（230）中选择的数据采集的数据中。 还公开了其它电路，设备，系统，操作过程和制造过程。

公开(公告)号：US20150212152A1

公开(公告)日：2015-07-30

申请号：US14605354

申请日：2015-01-26

Applicant: Texas Instruments Incorporated

Inventor： Khushboo Agarwal ,  Sanjay Krishna H V ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

IPC: G01R31/3177

CPC classification number: G01R31/31721 ,  G01R31/31707 ,  G01R31/31727

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Abstract translation: 用于测试专用集成电路（ASIC）的方法。 创建一组表示，覆盖用于测试模式功率分析的ASIC的关键子芯片中的一组时钟门的功率密度信息和时钟门物理位置。 基于所述一组表示的重叠，所述表示集合进一步分组成各个组。 然后，在高速测试操作模式期间，对应于该组时钟门限中的每一个产生一组测试控制信号，使得每个具有重叠表示的时钟门接收不同的测试控制信号。 此外，使用虚拟约束函数生成模式以选择性地启用该组测试控制信号，使得该组测试控制信号不被同时激活。

公开(公告)号：US20140208177A1

公开(公告)日：2014-07-24

申请号：US13749623

申请日：2013-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US08671329B2

公开(公告)日：2014-03-11

申请号：US13860773

申请日：2013-04-11

Applicant: Texas Instruments Incorporated

Inventor： Sanjay Kumar ,  Amit Kumar Dutta ,  Rubin A. Parekhji ,  Srivaths Ravi

IPC: G11C29/00

CPC classification number: G06F11/1008 ,  G06F11/1052 ,  G11C8/06 ,  G11C8/16 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/19

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路（110）一起使用的电子电路（200）。 电子电路（200）包括可在地址处访问的存储器电路（230），地址缓冲器（410），耦合到存储器电路（230）的数据缓冲器（440）和可在虚拟器件中操作的控制电路 循环，从存储器电路（230）中的下一个地址位置将数据从存储器电路（230）读取到数据缓冲器（440），并将该下一个地址存储在地址缓冲器（410）中。 电子电路还包括多路复用器（430），响应给定地址的比较电路（420）和地址缓冲器（410）中存储的地址，以操作多路复用器（430）以从数据缓冲器（440）传送数据 ）或者从存储器电路（230）传递数据; 以及混合器电路（450），其可操作以将所述部分写入数据部分放入从所述数据缓冲器（440）或存储器电路（230）中选择的数据采集的数据中。 还公开了其它电路，设备，系统，操作过程和制造过程。

公开(公告)号：US08839063B2

公开(公告)日：2014-09-16

申请号：US13749623

申请日：2013-01-24

Applicant: Texas Instruments Incorporated

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US11333707B2

公开(公告)日：2022-05-17

申请号：US16703909

申请日：2019-12-05

Applicant: Texas Instruments Incorporated

Inventor： Khushboo Agarwal ,  Sanjay Krishna Hulical Vijayaraghavachar ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

IPC: G06F30/33 ,  G01R31/317

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.