公开(公告)号：US20240178846A1

公开(公告)日：2024-05-30

申请号：US18435323

申请日：2024-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankit Garg ,  Abhijit Patki

IPC: H03L7/08 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

CPC classification number: H03L7/0807 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

Abstract: A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.

公开(公告)号：US20250110686A1

公开(公告)日：2025-04-03

申请号：US18476420

申请日：2023-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lokesh Kumar Botcha ,  Venkata Mohana Vamsi Voora ,  Ankit Garg ,  Supriyo Palit

IPC: G06F3/16

Abstract: An apparatus includes an amplifier having an input. An interface has inputs and an output. The interface is configured to: invert each bit of a value received at a first input of the interface to produce an inverted value; and provide the inverted value at the output. A processor has an input coupled the output of the interface, has first output coupled to a second input of the interface, and has a second output coupled to the input of the amplifier. The processor is configured to determine whether to set an adjustable gain setting of an audio processing block to the inverted value.

公开(公告)号：US11929751B1

公开(公告)日：2024-03-12

申请号：US18148652

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankit Garg ,  Abhijit Patki

IPC: H03L7/08 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

CPC classification number: H03L7/0807 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

Abstract: A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.