公开(公告)号：US20200135290A1

公开(公告)日：2020-04-30

申请号：US16271660

申请日：2019-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Nikita NARESH ,  Prathyusha Teja INUGANTI ,  Rakesh Channabasappa YARADUYATHINAHALLI ,  Aravinda ACHARYA ,  Jasbir SINGH ,  Naveen Ambalametil NARAYANAN

IPC: G11C29/38

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.