公开(公告)号：US20220091928A1

公开(公告)日：2022-03-24

申请号：US17027888

申请日：2020-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Desmond FERNANDES ,  Indu PRATHAPAN ,  Jasbir SINGH ,  Prathap SRINIVASAN ,  Rishav KARKI

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/40

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

公开(公告)号：US20240388466A1

公开(公告)日：2024-11-21

申请号：US18780705

申请日：2024-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir SINGH ,  Brian GINSBURG

IPC: H04L12/40 ,  G06F16/28

Abstract: Systems and methods are provided for testing driver assistance components and systems. Testing may involve using different types of data received at different virtual channel ports of a serial interface, in which each port receives a particular type of data, which data are then routed to different destination components using a table mapping each virtual channel port to a particular destination component. In another aspect, an update packet is used to modify a current version of the table, which maps each virtual channel port of a set of virtual channel ports to at least one of multiple destination components, to generate an updated version of the table, which is then used for routing subsequently received packets. A data modification module (DMM), which is one of the multiple destination components, may be used in the update process.

公开(公告)号：US20200135290A1

公开(公告)日：2020-04-30

申请号：US16271660

申请日：2019-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Nikita NARESH ,  Prathyusha Teja INUGANTI ,  Rakesh Channabasappa YARADUYATHINAHALLI ,  Aravinda ACHARYA ,  Jasbir SINGH ,  Naveen Ambalametil NARAYANAN

IPC: G11C29/38

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US20230324538A1

公开(公告)日：2023-10-12

申请号：US18322805

申请日：2023-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir SINGH

IPC: G01S7/35 ,  G01S13/58 ,  G01S13/02

CPC classification number: G01S13/584 ,  G01S7/352 ,  G01S13/0209 ,  G01S13/931

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas. The instructions direct the processor to iteratively access a NxM range matrix indexed by N velocity bins and M antenna combinations to obtain unique XxY range slices of the NxM range matrix, in which X is a lesser multiple of N and Y is a lesser multiple of M; iteratively access a MxS steering matrix indexed by the M antenna combinations and S hypothesis angles to obtain unique YxZ steering vector slices of the MxS steering matrix, in which Z is a lesser multiple of S; combine the first XxY range slice with the first YxZ steering vector slice to form an intermediate slice, combine each subsequently accessed XxY range slice and corresponding YxZ steering vector slice and add the combination to the intermediate slice until a beamforming slice is formed that incorporates data for all M antenna combinations for the particular set of X velocity bins and Z hypothesis angles. An operation is then performed on the beamforming slice.

公开(公告)号：US20220146660A1

公开(公告)日：2022-05-12

申请号：US17094338

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir SINGH

IPC: G01S13/58 ,  G01S13/02 ,  G01S7/35

Abstract: A non-transitory computer-readable medium stores instructions that cause processors to obtain an N×M range matrix comprising radar data indexed by velocity and antenna and an M×S steering matrix comprising expected phases indexed by antenna and hypothesis angle. For each unique X×Y range slice corresponding to a particular set of X velocities, processors store the particular range slice in a first buffer. For each unique Y×Z steering slice corresponding to a particular set of Y antenna, processors store the particular steering slice in a second buffer. The processors perform beamforming operations on the range, steering, and intermediate slices, storing the result in a third buffer as the intermediate slice. After each steering and range slice for the particular set of X velocities has been iterated through, the processors store the intermediate slice as a beamforming slice for the particular set of X velocities and the hypothesis angles.

公开(公告)号：US20210281440A1

公开(公告)日：2021-09-09

申请号：US17192271

申请日：2021-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir SINGH ,  Brian GINSBURG

IPC: H04L12/40 ,  G06F16/28

Abstract: A method includes receiving first data at a controller of an ADAS via a first virtual channel of a camera serial interface 2 (CSI-2) data interface. The method also includes receiving second data at the controller of the ADAS via a second virtual channel of the CSI-2 data interface. The method includes storing the first data at a first address in a memory, the first address specified by the first virtual channel. The method also includes storing the second data at a second address of a control register, the control register specified by the second data. The method includes performing a test using the first data and the second data.