公开(公告)号：US20200135290A1

公开(公告)日：2020-04-30

申请号：US16271660

申请日：2019-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Nikita NARESH ,  Prathyusha Teja INUGANTI ,  Rakesh Channabasappa YARADUYATHINAHALLI ,  Aravinda ACHARYA ,  Jasbir SINGH ,  Naveen Ambalametil NARAYANAN

IPC: G11C29/38

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US20210055345A1

公开(公告)日：2021-02-25

申请号：US17093702

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Nikita NARESH

IPC: G01R31/3177 ,  G01R31/317

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

公开(公告)号：US20210311121A1

公开(公告)日：2021-10-07

申请号：US17353882

申请日：2021-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Wilson PRADEEP

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

公开(公告)号：US20200309851A1

公开(公告)日：2020-10-01

申请号：US16372252

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash NARAYANAN ,  Nikita NARESH

IPC: G01R31/3177 ,  G01R31/317

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.