公开(公告)号：US10608650B2

公开(公告)日：2020-03-31

申请号：US16002881

申请日：2018-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arlo James Aude ,  Soumya Chandramouli ,  Roland Nii Ofei Ribeiro ,  Abishek Manian

IPC: H03B5/04 ,  H03B5/12 ,  H03L1/02 ,  H03L7/099 ,  H02M3/07

Abstract: In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.

公开(公告)号：US20200336288A1

公开(公告)日：2020-10-22

申请号：US16916968

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eleazar Walter Kenyon ,  Arlo James Aude

IPC: H04L7/033

Abstract: A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

公开(公告)号：US10742391B1

公开(公告)日：2020-08-11

申请号：US16359026

申请日：2019-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eleazar Walter Kenyon ,  Arlo James Aude

IPC: H04L7/033

Abstract: A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

公开(公告)号：US10734956B1

公开(公告)日：2020-08-04

申请号：US16675779

申请日：2019-11-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arlo James Aude ,  Eleazar Walter Kenyon ,  Kumar Anurag Shrivastava

IPC: H03F3/45 ,  H03K5/24 ,  H04B1/16 ,  H03K3/037 ,  H04B1/04

Abstract: A signal detection circuit includes a signal input terminal, a rectifier circuit, a comparator circuit; a current source, and a comparator output terminal. The rectifier circuit is coupled to the signal input terminal and is configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit is coupled to the rectifier circuit and is configured to receive a common mode signal and to generate a difference current based on a difference of the common mode signal and the rectified signal. The current source is coupled to the comparator circuit and is configured to generate a reference current. The comparator output terminal is configured to provide an output signal based on a difference of the reference current and the difference current.

公开(公告)号：US10944543B2

公开(公告)日：2021-03-09

申请号：US16916968

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eleazar Walter Kenyon ,  Arlo James Aude

IPC: H04L7/033

Abstract: A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.