Circuits and methods for asymmetric aging prevention
    2.
    发明授权
    Circuits and methods for asymmetric aging prevention 有权
    不对称老化预防的电路和方法

    公开(公告)号:US08890588B2

    公开(公告)日:2014-11-18

    申请号:US13852326

    申请日:2013-03-28

    CPC classification number: G06F1/24 G06F1/04 G06F1/06

    Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

    Abstract translation: 在一个实施例中,在集成电路(IC)中配置用于非对称衰减防止的电路包括主时钟,其被配置为产生主时钟信号,辅时钟被配置为产生辅时钟信号,状态确定电路和控制电路 。 状态确定电路被配置为确定与IC中的主时钟条件和上电复位状态中的至少一个相关联的当前工作状态。 控制电路被配置为响应于第一操作状态的确定而产生控制信号。 控制信号被配置为在确定第一操作状态时促进从主时钟到次时钟的转换,以及在确定第二操作状态时从安全操作模式转换到正常操作模式。 次级时钟与IC的安全工作模式相关联。

    Adaptive voltage scaling using temperature and performance sensors

    公开(公告)号:US12301229B2

    公开(公告)日:2025-05-13

    申请号:US16369360

    申请日:2019-03-29

    Abstract: An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

    ADAPTIVE VOLTAGE SCALING USING TEMPERATURE AND PERFORMANCE SENSORS

    公开(公告)号:US20190229732A1

    公开(公告)日:2019-07-25

    申请号:US16369360

    申请日:2019-03-29

    Abstract: An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

    CIRCUITS AND METHODS FOR ASYMMETRIC AGING PREVENTION
    7.
    发明申请
    CIRCUITS AND METHODS FOR ASYMMETRIC AGING PREVENTION 有权
    不对称老化预防的电路和方法

    公开(公告)号:US20140292383A1

    公开(公告)日:2014-10-02

    申请号:US13852326

    申请日:2013-03-28

    CPC classification number: G06F1/24 G06F1/04 G06F1/06

    Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

    Abstract translation: 在一个实施例中,在集成电路(IC)中配置用于非对称衰减防止的电路包括主时钟,其被配置为产生主时钟信号,辅时钟被配置为产生辅时钟信号,状态确定电路和控制电路 。 状态确定电路被配置为确定与IC中的主时钟条件和上电复位状态中的至少一个相关联的当前工作状态。 控制电路被配置为响应于第一操作状态的确定而产生控制信号。 控制信号被配置为在确定第一操作状态时促进从主时钟到次时钟的转换,以及在确定第二操作状态时从安全操作模式转换到正常操作模式。 次级时钟与IC的安全工作模式相关联。

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