公开(公告)号：US20210241820A1

公开(公告)日：2021-08-05

申请号：US17162842

申请日：2021-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Avishek BISWAS ,  Mahesh Madhukar MEHENDALE

IPC: G11C11/4094 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/4074 ,  G11C5/06

Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.

公开(公告)号：US20210240441A1

公开(公告)日：2021-08-05

申请号：US17162694

申请日：2021-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Avishek BISWAS ,  Mahesh Madhukar MEHENDALE ,  Hetul SANGHVI

IPC: G06F7/52 ,  G06N3/04

Abstract: A device includes a bit cell having first and second terminals, a first bit line coupled to the first terminal, a second bit line coupled to the second terminal, a first capacitor, a second capacitor, and a multiply and average (MAV) circuit coupled to the first capacitor, to the second capacitor, to the first bit line, and to the second bit line. The MAV circuit includes a first transistor coupled to the first capacitor and to a ground terminal and a second transistor coupled to the second capacitor and to the ground terminal. The first transistor has a first transistor control terminal selectively coupled to the first bit line and the second transistor has a second transistor control terminal selectively coupled to the second bit line.