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公开(公告)号：US09170956B2
公开(公告)日：2015-10-27
申请号：US13896941
申请日：2013-05-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Balatripura Sodemma Chavali , Karl Friedrich Greb , Rajeev Suvarna
CPC classification number: G06F13/4068 , G06F12/1416 , G06F12/1458 , G06F12/1483 , G06F13/1605 , G06F13/4221 , G06F2212/1016 , G06F2212/1052
Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.
Abstract translation: 一个包含硬件逻辑的存储器保护单元。 硬件逻辑从针对总线从设备的虚拟中央处理单元（CPU）接收事务，该事务与虚拟CPU标识（ID）相关联，其中虚拟CPU在物理CPU上实现。 硬件逻辑还根据虚拟CPU ID确定是否准予或拒绝对总线从站的访问。 虚拟CPU ID与实现虚拟CPU的物理CPU的ID不同。
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公开(公告)号：US20140223052A1
公开(公告)日：2014-08-07
申请号：US14015690
申请日：2013-08-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Balatripura Sodemma Chavali , Karl Fredrich Greb , Rajeev Suvarna
IPC: G06F13/16
CPC classification number: G06F13/4068 , G06F12/1416 , G06F12/1458 , G06F12/1483 , G06F13/1605 , G06F13/4221 , G06F2212/1016 , G06F2212/1052
Abstract: A system includes a bus slave coupled to a plurality of bus masters via one or more interconnects. The system also includes a memory protection unit (MPU) associated with the bus slave, the MPU having a set of access permissions that grants access to the bus slave from a first bus master and denies access to the bus slave from a second bus master. The MPU generates an error response as result of a transaction generated by a task on the second bus master attempting to access the bus slave.
Abstract translation: 系统包括经由一个或多个互连耦合到多个总线主机的总线从设备。 该系统还包括与总线从站相关联的存储器保护单元（MPU），MPU具有一组访问权限，其允许从第一总线主机访问总线从站，并拒绝从第二总线主站访问总线从站。 MPU由第二总线主机上尝试访问总线从站的任务生成的事务的结果生成错误响应。
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公开(公告)号：US09489332B2
公开(公告)日：2016-11-08
申请号：US14827077
申请日：2015-08-14
Applicant: Texas Instruments Incorporated
Inventor： Balatripura Sodemma Chavali , Karl Friedrich Greb , Rajeev Suvarna
CPC classification number: G06F13/4068 , G06F12/1416 , G06F12/1458 , G06F12/1483 , G06F13/1605 , G06F13/4221 , G06F2212/1016 , G06F2212/1052
Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.
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公开(公告)号：US20150356046A1
公开(公告)日：2015-12-10
申请号：US14827077
申请日：2015-08-14
Applicant: Texas Instruments Incorporated
Inventor： Balatripura Sodemma Chavali , Karl Friedrich Greb , Rajeev Suvarna
CPC classification number: G06F13/4068 , G06F12/1416 , G06F12/1458 , G06F12/1483 , G06F13/1605 , G06F13/4221 , G06F2212/1016 , G06F2212/1052
Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.
Abstract translation: 一个包含硬件逻辑的存储器保护单元。 硬件逻辑从针对总线从设备的虚拟中央处理单元（CPU）接收事务，该事务与虚拟CPU标识（ID）相关联，其中虚拟CPU在物理CPU上实现。 硬件逻辑还根据虚拟CPU ID确定是否准予或拒绝对总线从站的访问。 虚拟CPU ID与实现虚拟CPU的物理CPU的ID不同。
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