公开(公告)号：US20170147423A9

公开(公告)日：2017-05-25

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

公开(公告)号：US09170956B2

公开(公告)日：2015-10-27

申请号：US13896941

申请日：2013-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Balatripura Sodemma Chavali ,  Karl Friedrich Greb ,  Rajeev Suvarna

IPC: G06F12/00 ,  G06F12/14 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract translation: 一个包含硬件逻辑的存储器保护单元。 硬件逻辑从针对总线从设备的虚拟中央处理单元（CPU）接收事务，该事务与虚拟CPU标识（ID）相关联，其中虚拟CPU在物理CPU上实现。 硬件逻辑还根据虚拟CPU ID确定是否准予或拒绝对总线从站的访问。 虚拟CPU ID与实现虚拟CPU的物理CPU的ID不同。

公开(公告)号：US20150143181A1

公开(公告)日：2015-05-21

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract translation: 电子电路包括微处理器（410），与处理器耦合的外围设备（420），与处理器和外围设备耦合的端电路（470），以选择性地提供不同的端对端操作模式;以及检测电路（140） 检测到无法选择给定的字节码，从而避免了由于故障导致的无意识切换。 还公开了其它电路，装置，系统，操作方法和制造方法。

公开(公告)号：US20140173548A1

公开(公告)日：2014-06-19

申请号：US14020802

申请日：2013-09-07

Applicant: Texas Instruments Incorporated

Inventor： Karl Friedrich Greb ,  Abhishek Arora ,  Riccardo Mariani Yogitech

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F11/008

Abstract: A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool then automatedly performs a functional safety analysis based on the information regarding the user's specific implementation of the integrated circuit device. In one embodiment, the customer specifies specific functional modules of the integrated circuit device, and the tool performs a functional safety analysis of the integrated circuit device that considers the functional modules selected by the user. In another embodiment, the customer specifies diagnostic measures that are implemented in the user's application of the integrated circuit device, and the tool automatedly performs a functional safety analysis of the integrated circuit device taking into account the diagnostic measures selected by the user.

Abstract translation: 一种用于对根据客户的特定应用和设备的实现进行定制的集成电路设备的功能安全分析的工具。 关于给定集成电路设备的用户特定实现的信息由客户提供给安全分析工具的输入。 然后，该工具基于关于集成电路设备的用户具体实现的信息自动执行功能安全性分析。 在一个实施例中，客户指定集成电路设备的特定功能模块，并且该工具执行考虑由用户选择的功能模块的集成电路设备的功能安全分析。 在另一个实施例中，客户指定在用户的集成电路设备的应用中实现的诊断措施，并且该工具考虑了用户选择的诊断措施，自动执行集成电路设备的功能安全分析。

公开(公告)号：US09710318B2

公开(公告)日：2017-07-18

申请号：US14602933

申请日：2015-01-22

Applicant: Texas Instruments Incorporated

Inventor： Yanyang Xiao ,  Alexandre Pierre Palus ,  Karl Friedrich Greb ,  Kevin Patrick Lavery ,  Paul Krause

IPC: G06F11/07 ,  G11C29/52 ,  G11C29/00 ,  G11C29/48 ,  G06F11/10 ,  G11C29/14 ,  H03M13/27 ,  G06F13/40 ,  G06K9/00 ,  G06F9/30 ,  G06F11/28 ,  G06F11/16 ,  H03M13/13 ,  G11C29/04

CPC classification number: G06F11/0763 ,  G06F9/3004 ,  G06F9/30076 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/28 ,  G06F13/4013 ,  G06K9/00986 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13 ,  H03M13/27

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

公开(公告)号：US09489332B2

公开(公告)日：2016-11-08

申请号：US14827077

申请日：2015-08-14

Applicant: Texas Instruments Incorporated

Inventor： Balatripura Sodemma Chavali ,  Karl Friedrich Greb ,  Rajeev Suvarna

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/14 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

公开(公告)号：US20150356046A1

公开(公告)日：2015-12-10

申请号：US14827077

申请日：2015-08-14

Applicant: Texas Instruments Incorporated

Inventor： Balatripura Sodemma Chavali ,  Karl Friedrich Greb ,  Rajeev Suvarna

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract translation: 一个包含硬件逻辑的存储器保护单元。 硬件逻辑从针对总线从设备的虚拟中央处理单元（CPU）接收事务，该事务与虚拟CPU标识（ID）相关联，其中虚拟CPU在物理CPU上实现。 硬件逻辑还根据虚拟CPU ID确定是否准予或拒绝对总线从站的访问。 虚拟CPU ID与实现虚拟CPU的物理CPU的ID不同。