EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER
    3.
    发明申请

    公开(公告)号:US20200073839A1

    公开(公告)日:2020-03-05

    申请号:US16404494

    申请日:2019-05-06

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

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