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公开(公告)号:US20210240648A1
公开(公告)日:2021-08-05
申请号:US17233677
申请日:2021-04-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing MAUNG , Bhupendra SHARMA , Huanzhang HUANG , Douglas Edward WENTE , Suzanne Mary VINING , Mustafa Ulvi ERDOGAN
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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公开(公告)号:US20200272590A1
公开(公告)日:2020-08-27
申请号:US15931762
申请日:2020-05-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing MAUNG , Bhupendra SHARMA , Huanzhang HUANG , Douglas Edward WENTE , Suzanne Mary VINING , Mustafa Ulvi ERDOGAN
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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公开(公告)号:US20200073839A1
公开(公告)日:2020-03-05
申请号:US16404494
申请日:2019-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing MAUNG , Douglas Edward WENTE , Mustafa Ulvi ERDOGAN , Huanzhang HUANG , Saurabh GOYAL , Bhupendra SHARMA
Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.
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公开(公告)号:US20200042488A1
公开(公告)日:2020-02-06
申请号:US16404461
申请日:2019-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing MAUNG , Saurabh GOYAL , Bhupendra SHARMA , Huanzhang HUANG , Douglas Edward WENTE , Suzanne Mary VINING , Mustafa Ulvi ERDOGAN
Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.
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公开(公告)号:US20200034323A1
公开(公告)日:2020-01-30
申请号:US16404433
申请日:2019-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing MAUNG , Bhupendra SHARMA , Huanzhang HUANG , Douglas Edward WENTE , Suzanne Mary VINING , Mustafa Ulvi ERDOGAN
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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