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    REDRIVER CAPABLE OF SWITCHING BETWEEN LINEAR AND LIMITED MODES
    3.
    发明申请
    REDRIVER CAPABLE OF SWITCHING BETWEEN LINEAR AND LIMITED MODES 有权

    公开(公告)号：US20220150445A1

    公开(公告)日：2022-05-12

    申请号：US17363158

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Charles Michael CAMPBELL ,  Mustafa Ulvi ERDOGAN ,  Douglas Edward WENTE ,  Sridhar RAMASWAMY

    IPC: H04N7/10 ,  H04N21/4363 ,  H04N21/442

    Abstract: A redriver system adapted for coupling to a first device and to a second device includes first and second transmitter drivers and a snoop circuit. The first transmitter driver has a first enable input. The second transmitter driver has a second enable input. The snoop circuit is coupled to the first and second enable inputs. The snoop circuit is configured to determine whether the first device and the second device are to operate according to a first protocol. Responsive to the snoop circuit determining that the first and second devices are to operate according to the first protocol, the snoop circuit enables the first transmitter driver and disables the second transmitter driver. Responsive to the snoop circuit determining that the first and second devices are not to operate according to the first protocol, the snoop circuit disables the first transmitter driver and enables the second transmitter driver.

    LOW POWER LOSS OF LOCK DETECTOR
    4.
    发明申请
    LOW POWER LOSS OF LOCK DETECTOR 有权
    低功耗锁定检测器

    公开(公告)号：US20150365094A1

    公开(公告)日：2015-12-17

    申请号：US14735757

    申请日：2015-06-10

    Applicant: Texas Instruments Incorporated

    Inventor： Mustafa Ulvi ERDOGAN ,  Sridhar RAMASWAMY ,  Bhavesh G. BHAKTA

    IPC: H03L7/095 ,  H03L7/087 ,  H04L7/04 ,  H03L7/089

    CPC classification number: H03L7/095 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H04L7/033 ,  H04L7/04

    Abstract: A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.

    Abstract translation: 锁定检测器的丢失包括逻辑门，耦合到逻辑门的电压 - 电流转换器，耦合到转换器的电容器和耦合到电容器的比较器。 逻辑门被配置为从相位检测器接收第一误差信号和第二误差信号，执行第一和第二误差信号的与功能，并产生栅极输出信号。 转换器被配置为接收栅极输出信号并产生代表栅极输出信号的电流脉冲流。 电容器被配置为接收电流脉冲流并产生代表电流脉冲流的DC信号。 比较器被配置为将DC信号与参考信号进行比较并输出锁定信号。

    PHASE DETECTOR AND RETIMER FOR CLOCK AND DATA RECOVERY CIRCUITS
    5.
    发明申请
    PHASE DETECTOR AND RETIMER FOR CLOCK AND DATA RECOVERY CIRCUITS 有权
    用于时钟和数据恢复电路的相位检测器和反相器

    公开(公告)号：US20160028537A1

    公开(公告)日：2016-01-28

    申请号：US14810087

    申请日：2015-07-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mustafa Ulvi ERDOGAN ,  Sridhar RAMASWAMY

    IPC: H04L7/033

    CPC classification number: H04L7/033 ,  H03L7/0816 ,  H04L7/0337 ,  H04L25/00

    Abstract: A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

    Abstract translation: 包括重定时器电路，耦合到重定时器电路的相移电路和耦合到重定时器电路和相移电路的误差信号产生电路的相位检测器和重新定时器电路。 重新定时器电路被配置为接收数据信号，并且基于时钟信号的第一相位和基于时钟信号的第二相位的第二重定时数据信号来生成第一重新定时数据信号。 相移电路被配置为接收数据信号并且相移数据信号以产生第一，第二，第三和第四相移数据信号。 误差信号生成电路被配置为基于第一和第二重定时数据信号以及第一，第二，第三和第四相移数据信号产生第一误差信号和第二误差信号。

    FAST ACQUISITION FREQUENCY DETECTOR
    6.
    发明申请
    FAST ACQUISITION FREQUENCY DETECTOR 有权
    快速采集频率检测器

    公开(公告)号：US20150349785A1

    公开(公告)日：2015-12-03

    申请号：US14726753

    申请日：2015-06-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mustafa Ulvi ERDOGAN ,  Sridhar RAMASWAMY

    IPC: H03L7/08 ,  H04L7/033 ,  H03L7/087

    CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H04L7/0004 ,  H04L7/033 ,  H04L7/0331

    Abstract: A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison.

    Abstract translation: 相位频率检测器（PFD）电路，包括二进制相位检测器和耦合到二进制相位检测器的三相检测器。 二值相位检测器被配置为基于PFD电路处于频率获取状态，将时钟信号与数据信号进行比较，并根据比较输出上下信号。 二进制相位检测器也被配置为基于PFD电路处于锁频状态而被禁用。 三元相位检测器被配置为将时钟信号与数据信号进行比较，并根据比较输出上，下和保持信号。

    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER
    7.
    发明申请
    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开

    公开(公告)号：US20200073839A1

    公开(公告)日：2020-03-05

    申请号：US16404494

    申请日：2019-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Douglas Edward WENTE ,  Mustafa Ulvi ERDOGAN ,  Huanzhang HUANG ,  Saurabh GOYAL ,  Bhupendra SHARMA

    IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

    HIGH SPEED CURRENT MODE LATCH
    10.
    发明申请
    HIGH SPEED CURRENT MODE LATCH 有权
    高速电流模式锁

    公开(公告)号：US20150349786A1

    公开(公告)日：2015-12-03

    申请号：US14727990

    申请日：2015-06-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mustafa Ulvi ERDOGAN

    IPC: H03L7/08 ,  H04L7/00 ,  H03L7/087

    CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H04L7/0045

    Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.

    Abstract translation: 电流模式逻辑（CML）锁存器，其包括耦合到第二晶体管的第一晶体管，耦合到第四晶体管的第三晶体管，连接到第一，第二，第三和第四晶体管的第一电容器， 与第一电容耦合并连接到第三和第四晶体管。 第一和第二晶体管被配置为接收数据信号。 第三和第四晶体管被配置为接收时钟信号。

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