公开(公告)号：US20240204644A1

公开(公告)日：2024-06-20

申请号：US18066781

申请日：2022-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chen Jiang ,  Zhenyu Yu ,  Longqi Li ,  Desheng Guo

IPC: H02M1/00

CPC classification number: H02M1/0022 ,  H02M1/0009

Abstract: A power converter includes a power converter circuit and a microcontroller that controls the power converter circuit. The microcontroller includes a power control unit and a processing unit. The power control unit adjusts the switching frequency of the power converter circuit based on thresholds of a resonant capacitor of the power converter circuit. The power control unit also generates event signals indicative of breaches of the thresholds by the resonant capacitor. When the processing unit receives an event signal from the power control unit indicative of a breach of one of the thresholds by the resonant capacitor, the processing unit determines whether the switching frequency falls outside a defined range based on the event signal. In response to determining that the switching frequency falls outside the defined range, the processing unit instructs the power control unit to clamp the switching frequency of the power converter circuit.

公开(公告)号：US11888482B2

公开(公告)日：2024-01-30

申请号：US17565110

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chen Jiang ,  Shamim Choudhury ,  Subrahmanya Bharathi Akondy

IPC: H03K3/00 ,  H03K3/017 ,  H03K3/023 ,  H03K4/08 ,  H03K17/56

CPC classification number: H03K3/017 ,  H03K3/023 ,  H03K4/08 ,  H03K17/56

Abstract: A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.

公开(公告)号：US12231039B2

公开(公告)日：2025-02-18

申请号：US18066781

申请日：2022-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chen Jiang ,  Zhenyu Yu ,  Longqi Li ,  Desheng Guo

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00

Abstract: A power converter includes a power converter circuit and a microcontroller that controls the power converter circuit. The microcontroller includes a power control unit and a processing unit. The power control unit adjusts the switching frequency of the power converter circuit based on thresholds of a resonant capacitor of the power converter circuit. The power control unit also generates event signals indicative of breaches of the thresholds by the resonant capacitor. When the processing unit receives an event signal from the power control unit indicative of a breach of one of the thresholds by the resonant capacitor, the processing unit determines whether the switching frequency falls outside a defined range based on the event signal. In response to determining that the switching frequency falls outside the defined range, the processing unit instructs the power control unit to clamp the switching frequency of the power converter circuit.

公开(公告)号：US20250030328A1

公开(公告)日：2025-01-23

申请号：US18356221

申请日：2023-07-21

Applicant: Texas Instruments Incorporated

Inventor： Aki Li ,  Desheng Guo ,  Chen Jiang ,  Qing Ye

IPC: H02M1/00 ,  H02M1/088 ,  H02M3/335

Abstract: In described examples, a device includes a pulse width modulation (PWM) control circuit and a burst mode logic circuit. An input of the burst mode logic circuit is coupled to an output of the PWM control circuit. The burst mode logic circuit is configured to receive a feedback signal from a secondary side of a power conversion circuit. The burst mode logic circuit is configured to suppress a sleep period of a burst mode in response to a magnitude of the feedback signal exceeding a nominal load threshold voltage. The PWM control circuit continues to operate in the burst mode while the burst mode logic circuit suppresses the sleep period.